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s3p7588x 4-bit risc microprocessor user's manual revision 0
important notice the information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein. samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes. this publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of samsung or others. samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages. "typical" parameters can and do vary in different applications. all operating parameters, including " typicals" must be validated for each customer application by the customer's technical experts. samsung products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, for other applications intended to support or sustain life, or for any other application in which the failure of the samsung product could create a situation where personal injury or death may occur. should the buyer purchase or use a samsung product for any such unintended or unauthorized application, the buyer shall indemnify and hold samsung and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, either directly or indirectly, any claim of personal injury or death that may be associated with such unintended or unauthorized use, even if such claim alleges that samsung was negligent regarding the design or manufacture of said product. s3p7588x 4-bit cmos microcontroller user's manual, revision 0 publication number: ? 2002 samsung electronics all rights reserved. no part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of samsung electronics. samsung electronics' microcontroller business has been awarded full iso-14001 certification (bvqi certificate no. 9330). all semiconductor products are designed and manufactured in accordance with the highest quality standards and objectives. samsung electronics co., ltd. san #24 nongseo-ri, giheung-eup yongin-city gyeonggi-do, korea c.p.o. box #37, suwon 449-900 tel: (82)-(31)-209-1999 fax: (82)-(31)-209-1899 home-page url: http:// www.samsungsemi.com/
s3p7588x microcontroller iii preface the s3p7588x microcontroller user's manual is designed for application designers and programmers who are using the s3p7588x microcontroller for application development. it is organized in two parts: part i programming model part ii hardware descriptions part i contains software-related information to familiarize you with the microcontroller's architecture, programming model, instruction set, and interrupt structure. it has six chapters: chapter 1 product overview chapter 2 address spaces chapter 3 addressing modes chapter 4 memory map chapter 5 instruction set chapter 6 oscillator circuits chapter 1, "product overview," is a high-level introduction to the s3p7588x with a general product description, and detailed information about individual pin characteristics and pin circuit types. chapter 2, "address spaces," explains the s3p7588x program and data memory, internal register file, and mapped control registers, and explains how to address them. chapter 2 also describes working register addressing, as well as system and user-defined stack operations. chapter 3, "addressing modes," contains detailed descriptions of the six addressing modes that are supported by the cpu. chapter 4, " memory map," contains overview tables for all mapped system and peripheral control register values, as well as detailed one-page descriptions in standard format. you can use these easy-to-read, alphabetically organized, register descriptions as a quick-reference source when writing programs. chapter 5, " instruction set," describes the s3p7588x interrupt structure in detail and further prepares you for additional information presented in the individual hardware module descriptions in part ii. chapter 6, " oscillator circuits," describes the features and conventions of the instruction set used for all s3p7- series microcontrollers. several summary tables are presented for orientation and reference. detailed descriptions of each instruction are presented in a standard format. each instruction description includes one or more practical examples of how to use the instruction when writing an application program. a basic familiarity with the information in part i will help you to understand the hardware module descriptions in part ii. if you are not yet familiar with the sam88rcri product family and are reading this manual for the first time, we recommend that you first read chapters 1?3 carefully. then, briefly look over the detailed information in chapters 4, 5, and 6. later, you can reference the information in part i as necessary. part ii contains detailed information about the peripheral components of the s3p7588x microcontrollers. also included in part ii are electrical, mechanical, otp, development tools and errata. it has ten chapters: chapter 7 caller id chapter 8 interrupts chapter 9 power down chapter 10 reset chapter 11 i/o ports chapter 12 timers and timer/counters chapter 13 dtmf generator chapter 14 electrical data chapter 15 mechanical data chapter 16 otp chapter 17 development tools chapter 18 errata two order forms are included at the back of this manual to facilitate customer order for s3p7588x microcon - trollers: the mask rom order form, and the mask option selection form. you can photocopy these forms, fill them out, and then forward them to your local samsung sales representative.

s3p7588x microcontroller v table of contents part i ? programming model chapter 1 product overview otp ................................ ................................ ................................ ................................ ......................... 1-1 features summary ................................ ................................ ................................ ................................ .. 1-2 block diagram ................................ ................................ ................................ ................................ ......... 1-3 pin assignments ................................ ................................ ................................ ................................ ...... 1-4 pin descriptions ................................ ................................ ................................ ................................ ....... 1-6 pin circuit diagrams ................................ ................................ ................................ ................................ 1-8 chapter 2 address spaces overview ................................ ................................ ................................ ................................ ................. 2-1 general-purpose program memory (rom) ................................ ................................ ...................... 2-1 data memory (ram) ................................ ................................ ................................ ....................... 2-7 stack operations ................................ ................................ ................................ ............................. 2-15 chapter 3 addressing modes overview ................................ ................................ ................................ ................................ ................. 3-1 enable memory bank settings ................................ ................................ ................................ ......... 3-4 select bank register (sb) ................................ ................................ ................................ ............... 3-5 direct and indirect addressing ................................ ................................ ................................ ......... 3-6 chapter 4 memory map overview ................................ ................................ ................................ ................................ ................. 4-1 register descriptions ................................ ................................ ................................ ....................... 4-4 chapter 5 instr uction set overview ................................ ................................ ................................ ................................ ................. 5-1 instruction set features ................................ ................................ ................................ ........................... 5-1 high-level summary ................................ ................................ ................................ ....................... 5-9 binary code summary ................................ ................................ ................................ .................... 5-14 instruction descriptions ................................ ................................ ................................ ................... 5-24 chapter 6 oscillator circuits overview ................................ ................................ ................................ ................................ ................. 6-1 clock control registers ................................ ................................ ................................ ................... 6-1 clock output mode register (clmod) ................................ ................................ ............................ 6-5 clock output circuit ................................ ................................ ................................ ........................ 6-6
vi s3p7588x microcontroller table of contents (continued) part ii ? hardware descriptions chapter 7 caller id overview ................................ ................................ ................................ ................................ ................ 7-1 application ................................ ................................ ................................ ................................ ...... 7-2 functional descriptions of caller id block ................................ ................................ ............................... 7-7 functional block diagram ................................ ................................ ................................ ............... 7-7 analog input and preprocessor ................................ ................................ ................................ ....... 7-8 cas tone detection ................................ ................................ ................................ ....................... 7-9 fsk reception ................................ ................................ ................................ ............................... 7-10 stutter dial tone (sdt) detector ................................ ................................ ................................ .. 7-12 bit transfer ................................ ................................ ................................ ................................ ..... 7-16 register maps of caller id block ................................ ................................ ................................ ............ 7-21 mode register (mode) ................................ ................................ ................................ .................. 7-22 function register (func) ................................ ................................ ................................ .............. 7-22 dtmf tone select register (dtmft) ................................ ................................ .............................. 7-23 guard time register (gtime) ................................ ................................ ................................ ........ 7-23 interrupt register (intr) ................................ ................................ ................................ ................ 7-23 status register (stat) ................................ ................................ ................................ ................... 7-24 fsk data register (fskdt) ................................ ................................ ................................ ........... 7-24 dtmf output gain control register (dtmfg) ................................ ................................ ................. 7-24 special control register (cont1) ................................ ................................ ................................ .. 7-25 special control register (cont2) ................................ ................................ ................................ .. 7-25 chapter 8 interrupts overview ................................ ................................ ................................ ................................ ................ 8-1 vectored interrupts ................................ ................................ ................................ ......................... 8-2 interrupt priority register (ipr) ................................ ................................ ................................ ....... 8-8 external interrupt 0 and 1 mode registers (continued) ................................ ................................ ... 8-10 external interrupt 2 mode register (imod2) ................................ ................................ ................... 8-11 interrupt flags ................................ ................................ ................................ ................................ 8-14 chapter 9 power ? down overview ................................ ................................ ................................ ................................ ................ 9-1 idle mode timing diagrams ................................ ................................ ................................ ............ 9-2 stop mode timing diagrams ................................ ................................ ................................ .......... 9-3 port pin configuration for power-down ................................ ................................ ........................... 9-4 recommended connections for unused pins ................................ ................................ ................. 9-5
s3p7588x microcontroller vii table of contents (continued) chapter 10 reset reset overview ................................ ................................ ................................ ................................ ................. 10-1 caller id reset signal ................................ ................................ ................................ ..................... 10-1 hardware reset values after reset ................................ ................................ ................................ . 10-2 chapter 11 i/o ports overview ................................ ................................ ................................ ................................ ................. 11-1 port mode flags (pm flags) ................................ ................................ ................................ ......... 11-3 pull-up resistor mode register (pumod) ................................ ................................ ...................... 11-4 n-channel open-drain mode register (pne) ................................ ................................ .................. 11-4 port 1 circuit diagram ................................ ................................ ................................ ..................... 11-5 port 2, 3, 6, 7, 8, and 9 circuit diagram ................................ ................................ ........................... 11-6 port 4, 5 circuit diagram ................................ ................................ ................................ ................. 11-7 chapter 12 timers and timer/counters overview ................................ ................................ ................................ ................................ ................. 12-1 basic timer (bt) ................................ ................................ ................................ ................................ ..... 12-2 overview ................................ ................................ ................................ ................................ ......... 12-2 basic timer mode register (bmod) ................................ ................................ ................................ 12-5 basic timer counter (bcnt) ................................ ................................ ................................ ........... 12-6 basic timer output enable flag (boe) ................................ ................................ ........................... 12-6 basic timer operation sequence ................................ ................................ ................................ .... 12-6 watchdog timer mode register (wdmod) ................................ ................................ ..................... 12-8 watchdog timer counter (wdcnt) ................................ ................................ ................................ 12-8 watchdog timer counter clear flag (wdtcf) ................................ ................................ ............... 12-8 8-bit timer/counters 0 and 1 (tc0, tc1) ................................ ................................ ................................ 12-10 overview ................................ ................................ ................................ ................................ ......... 12-10 tc function summary ................................ ................................ ................................ .................... 12-10 tc component summary ................................ ................................ ................................ ................ 12-11 tc enable/disable procedure ................................ ................................ ................................ ......... 12-12 tc programmable timer/counter function ................................ ................................ ..................... 12-13 tc operation sequence ................................ ................................ ................................ .................. 12-13 tc event counter function ................................ ................................ ................................ ............. 12-14 tc clock frequency output ................................ ................................ ................................ ............ 12-15 tc external input signal divider ................................ ................................ ................................ ..... 12-16 tc mode register (tmodn) ................................ ................................ ................................ ........... 12-17 tc counter register (tcntn) ................................ ................................ ................................ ........ 12-19 tc reference register (trefn) ................................ ................................ ................................ ..... 12-20 tc output latch (toln) ................................ ................................ ................................ ................. 12-20 watch timer ................................ ................................ ................................ ................................ ............ 12-22 overview ................................ ................................ ................................ ................................ ......... 12-22 watch timer mode register (wmod) ................................ ................................ ............................. 12-24
viii s3p7588x microcontroller table of contents (continued) chapter 13 dtmf generator overview ................................ ................................ ................................ ................................ ................ 13-1 dtmf mode register ................................ ................................ ................................ ........................ 13-2 dtmf gain register ................................ ................................ ................................ ......................... 13-3 rc filtering ................................ ................................ ................................ ................................ .... 13-3 chapter 14 electrical data overview ................................ ................................ ................................ ................................ ................ 14-1 chapter 15 mechanical data overview ................................ ................................ ................................ ................................ ................ 15-1 chapter 16 otp overview ................................ ................................ ................................ ................................ ................ 16-1 operating mode characteristics ................................ ................................ ................................ ...... 16-3 chapter 17 development tools overview ................................ ................................ ................................ ................................ ................ 17-1 otps ................................ ................................ ................................ ................................ ............... 17-1 chapter 18 errata revision 1.0 ................................ ................................ ................................ ................................ ............ 18-1 errata list ................................ ................................ ................................ ................................ ............... 18-1
s3p7588x microcontroller ix list of figures figure title page number number 1-1 s3p7588x simplified block diagram ................................ ................................ ...... 1-3 1-2 s3p7588x pin assignment diagrams (100-tqfp-1414) ................................ ........ 1-4 1-3 pin diagram of pellet type ................................ ................................ ..................... 1-5 1-4 pin circuit type a ................................ ................................ ................................ .. 1-8 1-5 pin circuit type b ................................ ................................ ................................ .. 1-8 1-6 pin circuit type b-1 ................................ ................................ ............................... 1-8 1-7 pin circuit type a-4 ................................ ................................ ............................... 1-8 1-8 pin circuit type c ................................ ................................ ................................ .. 1-8 1-9 pin circuit type d-2 ................................ ................................ ............................... 1-9 1-10 pin circuit type e-2 ................................ ................................ ............................... 1-9 1-11 pin circuit type d-4 ................................ ................................ ............................... 1-9 2-1 rom address structure ................................ ................................ .......................... 2-3 2-2 vector address map ................................ ................................ ............................... 2-3 2-3 data memory (ram) map ................................ ................................ ....................... 2-7 2-4 working register map ................................ ................................ ............................ 2- 10 2-5 register pair configuration ................................ ................................ ..................... 2-11 2-6 1-bit, 4-bit, and 8-bit accumulator ................................ ................................ .......... 2-12 2-7 push-type stack operations ................................ ................................ .................. 2-16 2-8 pop-type stack operations ................................ ................................ .................... 2-17 3-1 ram address structure ................................ ................................ .......................... 3-2 3-2 smb and srb values in the sb register ................................ ............................... 3-5 4-1 register description format ................................ ................................ ................... 4-5 6-1 clock circuit diagram ................................ ................................ ............................. 6-2 6-2 crystal/ceramic oscillator ................................ ................................ ...................... 6-3 6-3 external oscillator ................................ ................................ ................................ .. 6-3 6-4 clo output pin circuit diagram ................................ ................................ ............. 6-6 7-1 application diagram for s3p7588x development system with ks57c5208 smds 7-4 7-2 recommende d diagram for typical application ................................ ..................... 7-5 7-3 block diagram of cid module ................................ ................................ ................ 7-7 7-4 differential input buffer of s3p7588x ................................ ................................ ..... 7-8 7-5 single ended buffer of s3p7588x ................................ ................................ .......... 7-9 7-6 casdetect, casint and int related to the cas tone ................................ ............ 7-9 7-7 sequence to receive an fsk data byte ................................ ................................ 7-10 7-8 interrupt behavior of the fsk receiver with bomdc = 1 ................................ ....... 7-11 7-9 interrupt behavior of the fsk receiver with bomdc = 0 ................................ ....... 7-11 7-10 sdt detector operation ................................ ................................ ......................... 7-12 7-11 external component to generate lrin ................................ ................................ ... 7-13 7-12 behavior of signals on a lin e reversal ................................ ................................ .. 7-13 7-13 behavior of signals during ring ................................ ................................ ............. 7-14 7-14 start and stop conditions ................................ ................................ ....................... 7-16 7-15 bit transfer timing ................................ ................................ ................................ . 7-16 7-16 byte transmission and acknowledge ................................ ................................ ...... 7-17 7-17 write sequence of the serial interface ................................ ................................ ... 7-18
x s3p7588x microcontroller list of figures (continued) figure title page number number 7-18 (a) read sequence of the serial interface when new register start address is programmed ................................ ................................ ................................ ......... 7-19 7-18 (b) read sequence of the serial interface when no register start address is programmed ................................ ................................ ................................ ......... 7-19 8-1 interrupt execution f lowchart ................................ ................................ ................ 8-3 8-2 interrupt control circuit diagram ................................ ................................ ........... 8-4 8-3 interrupt control circuit diagram ................................ ................................ ........... 8-5 8-4 two-level interrupt handling ................................ ................................ ................. 8-6 8-5 multi-level interrupt handling ................................ ................................ ................ 8-7 8-6 circuit diagram for int0 and int1 pins ................................ ................................ . 8-10 8-7 circuit diagram for int2 and ks0?ks7 pins ................................ ......................... 8-12 9-1 timing when idle mode is released by reset ................................ .................... 9-2 9-2 timing when idle mode is released by an interrupt ................................ .............. 9-3 9-3 timing when stop mode is released by reset ................................ ................... 9-3 9-4 timing when stop mode is release by an interrupt ................................ .............. 9-3 10-1 timin g for oscillation stabilization after reset ................................ ................... 10-1 11-1 port 1 circuit diagram ................................ ................................ ........................... 11-5 11-2 port 2, 3, 6, 7, 8, and 9 circuit diagram ................................ ................................ . 11-6 11-3 port 4 and 5 circuit diagram ................................ ................................ ................. 11-7 12-1 basic timer circuit diagram ................................ ................................ .................. 12-4 12-2 tc circuit diagram ................................ ................................ ................................ 12-12 12-3 tc timing diagram ................................ ................................ ............................... 12-19 12-4 watch timer circuit diagram ................................ ................................ ................ 12-23 13-1 block diagram of dtmf generator ................................ ................................ ....... 13-1 14-1 stop mode release timing when initiated by reset ................................ .......... 14-8 14-2 stop mode release timing when initiated by interrupt request ........................... 14-8 14-3 a.c. timing measurement points (except for xin) ................................ ................. 14-9 14-4 clock timing measurement at xin ................................ ................................ ......... 14-9 14-5 tcl timing ................................ ................................ ................................ ........... 14-9 14-6 input timing for reset signal ................................ ................................ .............. 14-10 14-7 input timing for external interrupts and quasi-interrupts ................................ ....... 14-10 14-8 waveform for cas timing characteristics ................................ ............................ 14-12 14-9 waveform for sdt timing characteristics ................................ ............................ 14-13 14-10 timing constraints of start and stop condition ................................ ..................... 14-14 14-11 timing of sck and sdt during byte transmission ................................ ............... 14-14
s3p7588x microcontroller xi list of figures (concluded) figure title page number number 15-1 pin diagram of pellet type ................................ ................................ ..................... 15-1 15-2 100-tqfp-1414 package dimensions ................................ ................................ .... 15-2 16-1 s3p7588x pin assignments (100-tqfp-1414) ................................ ....................... 16-2 16-2 otp programming algorithm ................................ ................................ ................. 16-4 17-1 s3p7588x development system configuration ................................ ...................... 17-2 17-1 s3p7588x development system configuration (continued) ................................ ... 17-3 17-2 s3p7588x target board diagram ................................ ................................ .......... 17-4 17-3 pin assignment of 50-pin dip connector ................................ ............................... 17-8

s3p7588x microcontroller xiii list of tables table title page number number 1-1 s3p7588x pin descriptions ................................ ................................ .................... 1-6 1-1 s3p7588x pin descriptions (continued) ................................ ................................ . 1-7 2-1 program memory address ranges ................................ ................................ ......... 2-2 2-2 data memory organization and addressing ................................ ............................ 2-9 2-3 working register organization and addressing ................................ ...................... 2-11 2-4 bsc register organization ................................ ................................ ..................... 2-18 2-6 interrupt status flag bit settings ................................ ................................ ............ 2-20 2-7 valid carry flag manipulation instructions ................................ .............................. 2-23 3-1 ram addressing not affected by the emb value ................................ ................... 3-4 3-2 1-bit direct and indirect ram addressing ................................ ............................... 3-6 3-3 4-bit direct and indirect ram addressing ................................ ............................... 3-8 3-4 8-bit direct and indirect ram addressing ................................ ............................... 3-11 4-1 i/o map for memory bank 15 ................................ ................................ ................. 4-2 4-1 i/o map for memory bank 15 (continued) ................................ .............................. 4-3 4-1 i/o map for memory bank 15 (continued) ................................ .............................. 4-4 5-1 valid 1-byte instruction combinations for ref look-ups ................................ ....... 5-2 5-2 bit addressing modes and parameters ................................ ................................ ... 5-5 5-3 skip conditions for adc and sbc instructions ................................ ....................... 5-6 5-4 data type symbols ................................ ................................ ................................ 5-7 5-5 register identifiers ................................ ................................ ................................ . 5-7 5-6 instruction operand notation ................................ ................................ .................. 5-7 5-7 opcode definitions (direct) ................................ ................................ .................... 5-8 5-8 opcode definitions (indirect) ................................ ................................ .................. 5-8 5-9 cpu control instructions ? high-l evel summary ................................ .................. 5-10 5-10 program control instructions ? high-level summary ................................ ............ 5-10 5-11 data transfer instructions ? high-level summary ................................ ................ 5-11 5-12 logic instructions ? high-level summary ................................ ............................. 5-12 5-13 arithmetic instructions ? high-level summary ................................ ...................... 5-12 5-14 bit manipulation instructions ? high-level summary ................................ ............ 5-13 5-15 cpu control instructions ? binary code summary ................................ ............... 5-15 5-16 program control instructions ? binary code summary ................................ ......... 5-16 5-16 program control instructions ? binary code summary (continued) ...................... 5-17 5-17 data transfer instructions ? binary code summary ................................ .............. 5-17 5-17 data transfer instructions ? binary code summary (continued) ........................... 5-18 5-17 data transfer instructions ? binary code summary (concluded) .......................... 5-19 5-18 logic instructions ? binary code summary ................................ ........................... 5-19 5-19 arithmetic instructions ? binary code summary ................................ ................... 5-20 5-20 bit manipulation instructions ? binary code summary ................................ .......... 5-21 5-20 bit manipulation instructions ? binary code summary (continued) ....................... 5-22 5-20 bit manipulation instructions ? binary code summary (concluded) ...................... 5 -23
xiv s3p7588x microcontroller list of tables (continued) table title page number number 6-1 power control register (pcon) organization ................................ ........................ 6-4 6-2 instruction cycle times for cpu clock rates ................................ ........................ 6-5 6-3 clock output mode register (clmod) organization ................................ ............. 6-5 7-1 interconnections between internal mcu and caller id ................................ ........... 7-2 7-2 pin assignment in caller id mode ................................ ................................ ......... 7-3 7-3 pin configurations for selecting operation modes ................................ ................. 7-3 7-4 recommended external component values for typical application ...................... 7-6 7-5 cas detector parameters ................................ ................................ ..................... 7-9 7-6 fsk receiver parameters ................................ ................................ ..................... 7-10 7-7 stutter dial tone parameters ................................ ................................ ................ 7-12 7-8 dtmf frequencies code table ................................ ................................ ............. 7-15 7-9 bit specification of the address field ................................ ................................ .... 7-17 7-10 interrupt sources of the cid block ................................ ................................ ......... 7-20 7-11 register overview ................................ ................................ ................................ . 7-21 8-1 interrupt types and corresponding port pin(s) ................................ ...................... 8-1 8-2 is1 and is0 bit manipulation for multi-level interrupt handling ............................. 7 8-3 standard interrupt priorities ................................ ................................ ................... 8 8-4 interrupt priority register settings ................................ ................................ ......... 8 8-5 imod0 and imod1 register organization ................................ ............................. 9 8-6 imod2 register bit settings ................................ ................................ .................. 11 8-7 int errupt enable and interrupt request flag addresses ................................ ......... 14 8-8 interrupt request flag conditions and priorities ................................ .................... 15 9-1 hardware operation during power-down modes ................................ ................... 9-2 9-2 unused pin connections for reduced power consumption ................................ ... 9-5 10-1 hardware register values after reset ................................ ................................ 10-2 10-1 hardware register values after reset (continued) ................................ ............. 10-3 11-1 i/o port overview ................................ ................................ ................................ .. 11-1 11-1 i/o port overview (continued) ................................ ................................ ............... 11-2 11-2 port pin status during instruction execution ................................ .......................... 11-2 11-3 port mode group flags ................................ ................................ ......................... 11-3 11-4 pull-up res istor mode register (pumod) organization ................................ ........ 11-4 12-1 basic timer register overview ................................ ................................ ............. 12-3 12-2 basic timer mode register (bmod) organization ................................ ................. 12-5 12-3 watchdog timer interval time ................................ ................................ .............. 12-8 12-4 tc register overview ................................ ................................ ........................... 12-11 12-5 tmodn settings for tcln edge detection ................................ ............................ 12-14 12-6 tc mode register (tmodn) organization ................................ ............................. 12-17 12-7 tmodn.6, tmodn.5, and tmodn.4 bit settings ................................ ................... 12-18 12-8 watch timer mode register (wmod) organization ................................ .............. 12-24
s3p7588x microcontroller xv list of tables (continued) table title page number number 13-1 keyboard arrangement ................................ ................................ ........................... 13-2 13-2 tone output frequencies ................................ ................................ ....................... 13-2 13-3 dtmf mode register (dtmr) organization ................................ ........................... 13-2 13-4 dtmr.7?dtmr.4 key input control settings ................................ .......................... 13-3 13-5 dtmf gain register (dtgr) organization ................................ ............................ 13-3 14-1 absolute maximum ratings ................................ ................................ .................... 14-2 14-2 d.c. electrical characteristics ................................ ................................ ................ 14-2 14-2 d.c. electrical characteristics (continued) ................................ ............................. 14-3 14-2 d.c. electrical char acteristics (continued) ................................ ............................. 14-4 14-3 main system clock oscillator characteristics ................................ ......................... 14-5 14-4 input/output capacitance ................................ ................................ ....................... 14-6 14-5 a.c. electrical characteristics ................................ ................................ ................ 14-6 14-6 ram data retention supply voltage in stop mode ................................ ................ 14-7 14-7 electrical characteristics of cid block ................................ ................................ .... 14-11 14-8 cas timing characteristics ................................ ................................ .................... 14-12 14-9 sdt timing characteristics ................................ ................................ .................... 14-12 14-10 serial interface timing characteristics ................................ ................................ ... 14-13 16-1 s3p7588x pin descriptions used to read/write the eprom ................................ . 15-3 16-2 s3p7588x features ................................ ................................ ............................... 15-3 16-3 operat ing mode selection criteria ................................ ................................ .......... 15-3 17-1 switch settings for power configuration ................................ ................................ . 17-5 17-1 switch settings for power configuration (continued) ................................ .............. 17-6 17-2 switch settings for user clock selection ................................ ................................ 17-7 17-3 switch settings for reset signal of caller id ................................ .......................... 17-7

s3p7588x microcontroller xvii list of programming tips description page number chapter 2: address spaces defining vectored interrupts ................................ ................................ ................................ .................... 2-4 using the ref look-up table ................................ ................................ ................................ ................. 2-6 clearing data memory banks 0 and 1 ................................ ................................ ................................ ...... 2-9 selecting the working register area ................................ ................................ ................................ ....... 2-13 selecting the working register area ................................ ................................ ................................ ....... 2-14 initializing the stack pointer ................................ ................................ ................................ ..................... 2-15 using the bsc register to output 16-bit data ................................ ................................ ......................... 2-18 setting isx flags for interrupt processing ................................ ................................ ................................ 2-20 using the emb flag to select memory banks ................................ ................................ .......................... 2-21 using the erb flag to select register banks ................................ ................................ .......................... 2-22 using the carry flag as a 1-bit accumulator ................................ ................................ ............................ 2-24 chapter 3: addressing mode initializing the emb and erb flags ................................ ................................ ................................ ......... 3-3 1-bit addressing modes ................................ ................................ ................................ ........................... 3-7 4-bit addressing modes ................................ ................................ ................................ ........................... 3-8 4-bit addressing modes (continued) ................................ ................................ ................................ ........ 3-9 4-bit addressing modes (continued) ................................ ................................ ................................ ........ 3-10 8-bit addressing modes ................................ ................................ ................................ ........................... 3-12
product overview s3 p7588x 1- 1 1 product overview the s3p7588x single-chip cmos microcontroller has been designed for high-performance using sam 47 ( samsung arrangeable microcontrollers). sam 47, samsung's newest 4-bit cpu core is notable for its low energy consumption and low operating voltage. with it's dtmf generator, watchdog timer function, versatile 8-bit timer/counters, and caller id module the s3p7588x offers an excellent design solution for a wide variety of telecommunication applications. up to 25 pins of the available 100-pin tqfp package can be assign to i/o. six vectored interrupts provide fast response to internal and external events. in addition, the s3p7588x's advanced cmos technology provides for low power consumption and a wide operating voltage range. the s3p7588x has two package options, one is tqfp type and the other is pellet type. only pellet type can be ordered for mass production. the tqfp type is provided only for system software development. otp the s3p7588x microcontroller has an on-chip 8k-byte one-time- programable eprom instead of masked rom, which provides comfortable environments for new application development.
s3p7588x product overview 1- 2 features summary memory 768 4-bit ram 8,192 8-bit eprom 28 i/o pins input only: 3 pins i/o: 25 pins n-channel open-drain i/o: 8 pins memory-mapped i/o structure data memory bank 15 caller id 1200 baud fsk (frequency shift keying) demodulator with sensitivity -38dbm (600 w ) confirms to bell 202 and ccitt v.23 standards receive sensitivity of ?32dbm (in 600 w ) for cas (cpe alerting signal) stutter dial tone (sdt) detector with sensitivity of -36dbm ring or line reversal detector on-hook and off-hook applications according to bellcore tr-nwt-000030 and sr-tsv-002476 specifications compatible with etsi standards ets 300 659-1 and ets 3000 659-2 dtmf generator 16 dual-tone frequencies for tone dialing 8-bit basic timer programmable interval timer watchdog timer two 8-bit timer/counters programmable 8-bit timer external event counter function arbitrary clock frequency output watch timer real-time and interval time measurement four frequency outputs to the buz pin bi t sequential carrier supports 8-bit serial data transfer in arbitrary format interrupts 2 external interrupt vectors 4 internal interrupt vectors 2 quasi-interrupts power-down modes idle: only cpu clock stops stop: system clock stops oscillation sources crystal, or ceramic for main system clock main system clock frequency: 0.4?6.0mhz. 3.579545mhz is mandatory for caller id application cpu clock divider circuit (by 4, 8, or 64) instruction execution times 0.95, 1.91, and 15.3 m s at 4.19mhz 1.12, 2.23, 17.88 m s at 3.58mhz 0.67, 1.33, 10.7 m s at 6.0mhz operating temperature 0 c to 70 c operating voltage range 3.0v to 5.5v package types 100-tqfp-1414 (only for system development) pellet version is available (for mass production)
product overview s 3p7588x 1- 3 block diagram basic timer main osc watch timer 8-bit timer/ counter 0 8-kbyte program rom 768 x 4-bit data memory cas/sdt/fsk receiver serial interface lr/ring detector 14-bit a/d converter xin xout p1.3/int4 inp inn out vref generator vref ins resetb test lrin sam47 cpu i/o port and interrupt control p1.1/int1 p6.0-p6.3/ ks0-ks3 watchdog timer 8-bit timer/ counter 1 i/o port 6 i/o port 7 i/o port 9 p7.0-p7.3/ ks4-ks7 p9.0 test & internal connection logic input port 1 dtmf generator i/o port 3 p1.2/int2 p3.3 p3.2 p3.0/tcl0 p4.1-p4.3 p2.0/tclo0 i/o port 5 p5.0-p5.3 dtmf i/o port 4 p4.0/btco cid core ks57c5208 core i/o port 2 p2.3/buz p3.1/tcl1 p9.1/tclo1 p9.2/clo figure 1-1. s3p7588x simplified block diagram
s3p7588x product ov erview 1- 4 pin assignments nc nc nc nc v ssa out inn inp ins vref v dda lrin dtmf p7.3/ks7 p7.2/ks6 p7.1/ks5 p7.0/ks4 p6.3/ks3 p6.2/ks2 p6.1/ks1 p6.0/ks0 p5.3 p5.2 p5.1 p5.0 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 s3p7588x 100-tqfp-1414 nc nc nc p9.0 p9.1/tclo1 p9.2/clo p1.1/int1 p1.2/int2 p1.3/int4 p2.0/tcl0/sda p3.0/tcl0/sda p3.1/tcl1/sck v dd v ss x out x in test p2.3/buz p3.2 resetb p3.3 p4.0/btco p4.1 p4.2 p4.3 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc figure 1-2. s3p7588x pin assignment diagrams (100-tqfp-1414)
product overview s 3p7588x 1- 5 44 pin pellet p9.0 p9.1 p9.2 p1.1 p1.2 p1.4 p2.0 p3.0 p3.1 v dd v ss test p3.2 reset p3.3 p4.0 p4.1 p4.2 p4.3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 xout xin p2.3 vref vdda lrin dtmf p7.3 p7.2 p7.1 p7.0 p6.3 p6.2 p6.1 p6.0 p5.3 p5.2 p5.1 p5.0 ins inp inn out vssa vssa 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 42 43 44 45 46 47 figure 1-3. pin diagram of pellet type
s3p7588x product ov erview 1- 6 pin descriptions table 1-1. s3p7588x pin descriptions pin name pin type reset value description pin number circuit type p1.1/int1 p1.2/int2 p1.3/int4 i i 3-bit input port of schmitt triggered type. 1-bit and 4-bit read and test is possible. each port has software assignable pull-up resistor. p1.1-p1.3 are alternatively used as external interrupt input pins. 7 8 9 a-4 p2.0/tclo0 p2.3/buz i/o i 2-bit i/o ports. 1-bit and 4-bit read/write and test is possible. each individual pin is software configurable as input or output. 2-bit pull-up resistors are software assignable to input pins and are automatically disabled for output pins. port 2 , port 3 can be paired to enable 6-bit data transfer. p2.0 is alternatively used as the clock outputs of timer/counter 0. p2.3 is alternatively used as 2khz , 4khz , 8khz , 16khz frequency output at the watch timer clock frequency of 4.19mhz. 10 18 d-2 p3.0/tcl0 p3.1/tcl1 p3.2 p3.3 i/o i 4-bit pull-up resistors are software assignable to input pins and are automatically disabled for output pins. ports 2 and 3 can be paired to enable 8-bit data transfer. p3.0 , p3.1 are alternatively used as external clock input for timer/counter 0 , 1. 11 12 19 21 d-4 p4.0/btco p4.1-p4.3 p5.0?p5.3 i/o i 4-bit i/o ports. 1-bit and 4-bit read/write and test is possible. individual pins are software configurable as input or output. 4-bit pull-up resistors are software assignable to input pins and are automatically disabled for output pins. n-channel open-drain or push-pull output can be selected by software (1-bit unit) ports 4 and 5 can be paired to support 8-bit data transfer. 22 23-25 26-29 e-2
product overview s 3p7588x 1- 7 table 1-1. s3p7588x pin descriptions (continued) pin name pin type reset value description pin number circuit type p6.0?p6.3 /ks0-ks3 p7.0?p7.3 /ks4-ks7 i/o i 4-bit i/o ports. 1-bit and 4-bit read/write and test is possible. each individual pin can be assignable as input or output. 4-bit pull-up resistors are software assignable to input pins and are automatically disabled for output pins. port 6 , port 7 can be paired to enable 8-bit data transfer. port 6 , port 7 are alternatively used as two quasi-interrupt inputs with falling edge detection. 30-33 34-37 d-4 p9.0 p9.1/tclo1 p9.2/clo i/o i 4-bit i/o port. 1-bit or 4-bit read/write and test is possible. individual pins are software configurable as input or output. 3-bit pull-up resistors are software assignable to input pins and are automatically disabled for output pins. p9.2 is alternatively used as a clock output , and p9.1 is alternatively used as the clock output of timer/counter 1. 4 5 6 d-2 dtmf o ? dtmf output. 38 c inp i ? op-amp positive signal input for cas , fsk and sdt 43 inn i ? op-amp negative signal input for cas , fsk and sdt 44 ins i ? op-amp single-ended signal input for cas , fsk and sdt 42 out o ? op-amp output signal for cas , fsk and sdt 45 vref o ? reference voltage for op-amp signals 41 lrin i ? input for line reversal or ring detection 39 b-1 v dd ? ? digital power supply 13 ? v ss ? ? digital ground 14 ? v dda ? ? analog power supply 40 ? v ssa ? ? analog ground 46 ? resetb ? ? reset signal (low active) 20 b x in x out ? ? crystal, or ceramic oscillator signal for main system clock. (for external clock input, use x in and input x in 's reverse phase to x out ) 16 15 ? test ? ? test signal input (high active) 17 ? nc ? ? no connection ? ?
s3p7588x product ov erview 1- 8 pin circuit diagrams in v dd p-channel n-channel figure 1-4. pin circuit type a in v dd pull-up resistor schmitt trigger figure 1-5. pin circuit type b in schmitt trigger figure 1-6. pin circuit type b -1 in v dd pull-up resistor schmitt trigger resistor enable p-channel figure 1-7. pin circuit type a-4 v dd n-channel p-channel out data output disable figure 1-8. pin circuit type c
product overview s 3p7588x 1- 9 v dd output disable pull-up resistor i/o circuit type c p-channel data resistor enable figure 1-9. pin circuit type d-2 v dd output disable pull-up resistor i/o pull-up resistor enable data pne p-channel n-channel v dd figure 1-10. pin circuit type e-2 v dd output disable pull-up resistor i/o circuit type c p-channel data resistor enable schmitt triger figure 1-11. pin circuit type d-4
s3p7588x product ov erview 1- 10 notes
s3p7588x address spaces 2- 1 2 address spaces overview program rom maps for the s3p7588x are one time programmable at the application field. in its standard configuration, the device's 8,192 8-bit program memory have three areas that are directly addressable by the program counter (pc): ? 16-byte area for vector addresses ? 16-byte general-purpose area ? 96-byte instruction reference area ? 8,064-byte general-purpose area general-purpose program memory (rom) two program memory areas are allocated for general-purpose use: one area is 16 bytes in size and the other is 8,064 bytes. vector addresses a 16-byte vector address area is used to store the vector addresses required to execute system resets and interrupts. start addresses for interrupt service routines are stored in this area, along with the values of the enable memory bank (emb) and enable register bank (erb) flags that are used to initialize the corresponding service routines. the 16-byte area can be used alternately as general-purpose rom. ref instructions locations 0020h?007fh are used as a reference area (look-up table) for 1-byte ref instructions. the ref instruction reduces the byte size of instruction operands. ref can reference one 2 -byte instruction, two 1-byte instructions, and three-byte instructions which are stored in the look-up table. unused look-up table addresses can be used as general-purpose rom.
address spaces s3p7 588x 2- 2 table 2-1. program memory address ranges rom area function address ranges area size (in bytes) vector address area 0000h?000fh 16 general-purpose program memory 0010h?001fh 16 ref instruction look-up table area 0020h?007fh 96 general-purpose program memory 0080h?1fffh 8,064 general-purpose memory areas the 16-byte area at rom locations 0010h?001fh and the 8,064-byte area at rom locations 0080h?1fffh are used as general-purpose program memory. unused locations in the vector address area and ref instruction look-up table areas can be used as general-purpose program memory. however, care must be taken not to overwrite live data when writing programs that use special-purpose areas of the rom. vector address area the 16-byte vector address area of the rom is used to store the vector addresses for executing system resets and interrupts. the starting addresses of interrupt service routines are stored in this area, along with the enable memory bank (emb) and enable register bank (erb) flag values that are needed to initialize the service routines. 16-byte vector addresses are organized as follows: emb erb 0 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 to set up the vector address area for specific programs, use the instruction ventn. the programming tips on the next page explain how to do this.
s3p7588x address spaces 2- 3 vect address (16 bytes) general purpose area (16 bytes) instruction reference area (96 bytes) general purpose area (8,064 bytes) 0000h 000fh 0010h 001fh 0020h 007fh 0080h 1fffh figure 2-1. rom address structure 7 0000h 6 5 4 3 2 1 0 reset intb/int4 int0 (note) int1 not implemented intt0 intt1 not implemented (reserved for future use) (reserved for future use) 0002h 0004h 0006h 0008h 000ah 000ch 000eh figure 2-2. vector address map note: int0 is dedicated to caller id interrupt
address spaces s3p7 588x 2- 4 f f p rogramming tip ? defining vectored interrupts the following examples show you several ways you can define the vectored interrupt and instruction reference areas in program memory: 1. when all vector interrupts are used: org 0000h vent0 1,0,reset ; emb ? 1, erb ? 0; jump to reset address vent1 0,0,intb ; emb ? 0, erb ? 0; jump to intb address vent2 0,0,int0 ; emb ? 0, erb ? 0; jump to int0 address vent3 0,0,int1 ; emb ? 0, erb ? 0; jump to int1 address nop nop vent5 0,0,intt0 ; emb ? 0, erb ? 0; jump to intt0 address vent6 0,0,intt1 ; emb ? 0, erb ? 0; jump to intt1 address 2. when a specific vectored interrupt such as int0, and intt0 is not used, the unused vector interrupt locations must be s kipped with the assembly instruction org so that jumps will address the correct locations: org 0000h vent0 1,0,reset ; emb ? 1, erb ? 0; jump to reset address vent1 0,0,intb ; emb ? 0, erb ? 0; jump to intb address org 0006h ; int0 interrupt not used vent3 0,0,int1 ; emb ? 0, erb ? 0; jump to int1 address org 000ch ; intt0 interrupt not used vent6 0,0,intt1 ; emb ? 0, erb ? 0; jump to intt1 address org 0010h 3. if an int0 interrupt is not used and if its corresponding vector interrupt area is not fully utilized, or if it is not written by a org instruction as in example 2, a cpu malfunction will occur: org 0000h vent0 1,0,reset ; emb ? 1, erb ? 0; jump to reset address ven t1 0,0,intb ; emb ? 0, erb ? 0; jump to intb address vent3 0,0,int1 ; emb ? 0, erb ? 0; jump to int0 address nop nop vent5 0,0,intt0 ; emb ? 0, erb ? 0; jump to int1 address vent6 0,0,intt1 ; emb ? 0, erb ? 0; jump to intt0 address org 0010h
s3p7588x address spaces 2- 5 general-purpose rom area in this example, when an intt0 interrupt is generated, the corresponding vector area is not vent5 intt0, but vent6 intt1. this causes an intt0 interrupt to jump incorrectly to the intt1 address and causes a cpu malfunction to occur. instruction reference area using 1-byte ref instructions, you can easily reference instructions with larger byte sizes that are stored in addresses 0020h?007fh of program memory. this 96-byte area is called the ref instruction reference area, or look-up table. locations in the ref look-up table may contain two one-byte instructions, a single two-byte instruction, or three-byte instruction such as a jp (jump) or call. the starting address of the instruction you are referencing must always be an even number. to reference a jp or call instruction, it must be written to the reference area in a two-byte format: for jp, this format is tjp; for call, it is tcall. you can use ref instructions to execute instructions larger than one byte. there are tree ways you can use ref instruction: ? using the 1-byte ref instruction to execute one 2-byte or two 1-byte instructions, ? branching to any location by referencing a branch instruction stored in the look-up table, ? calling subroutines at any location by referencing a call instruction stored in the look-up table.
address spaces s3p7 588x 2- 6 f f programming tip ? using the ref look-up table here is one example of how to use the ref instruction look-up table: org 0020h jmain tjp main ; 0, main keyck btsf keyfg ; 1, keyfg check watch tcall clock ; 2, call clock inchl ld @hl,a ; 3, (hl) ? a incs hl ? ? ? abc ld ea,#00h ; 47, ea ? #00h org 0080 main nop nop ? ? ? ref keyck ; btsf keyfg (1-byte instruction) ref jmain ; keyfg = 1, jump to main (1-byte instruction) ref watch ; keyfg = 0, call clock (1-byte instruction) ref inchl ; ld @hl,a ; incs hl ref abc ; ld ea,#00h (1-byte instruction) ? ? ?
s3p7588x address spaces 2- 7 data memory (ram) overview in its standard configuration, the 896 4 -bit data memory has five areas: ? 32 4-bit working register area ? 224 4-bit general-purpose area (also used as stack area) ? 2 256 4-bit general-purpose area ? 128 4-bit area for peripheral hardware to make it easier to reference, the data memory area has four memory banks ? bank 0, bank 1, bank 2, and bank 15. the select memory bank instruction (smb) is used to select the bank you want to select as working data memory. data stored in ram locations are 1-, 4-, and 8-bit addressable. initialization values for the data memory area are not defined by hardware and must therefore be initialized by program software following resetb. however, when resetb signal is generated in power-down mode, the data memory contents are held. working registers (32 4 bits) general-purpose registers and stack area (224 4 bits) general-purpose registers (256 4 bits) general-purpose registers (256 4 bits) memory-mapped i/o aeeress registers (128 4 bits) bank 0 bank 1 bank 2 bank 15 000h 01fh 020h 0ffh 100h 1ffh 200h fffh 2ffh f80h figure 2-3. data memory (ram) map
address spaces s3p7 588x 2- 8 memory banks 0, 1, 2, and 15 bank 0 (000h?0ffh) the lowest 32 nibbles of bank 0 (000h?01fh) are used as working registers; the next 224 nibbles (020h?0ffh) can be used both as stack area and as general-purpose data memory. use the stack area for implementing subroutine calls and returns, and for interrupt processing. bank 1 (100h?1ffh) the 256 nibbles of bank 1 (100h?1ffh) are for general-purpose use. bank 2 (200h?2ffh) the 256 nibbles of bank 2 (200h?2ffh) are for general-purpose use bank 15 (f80h?fffh) the microcontroller uses bank 15 for memory-mapped peripheral i/o. fixed ram locations for each peripheral hardware register: the port latches, timers, peripherals controls, etc. are mapped into this area. data memory addressing modes the enable memory bank (emb) flag controls the addressing mode for data memory banks 0, 1, 2 or 15. when the emb flag is logic zero, the addressable area is restricted to specific locations, depending on whether direct or indirect addressing is used. with direct addressing, you can access locations 000h?07fh of bank 0 and bank 15. with indirect addressing, only bank 0 (000h?0ffh) can be accessed. when the emb flag is set to logic one, all four data memory banks can be accessed according to the current smb value. for 8-bit addressing, two 4-bit registers are addressed as a register pair. also, when using 8-bit instructions to address ram locations, remember to use the even-numbered register address as the instruction operand. working registers the ram working register area in data memory bank 0 is further divided into four register banks (bank 0, 1, 2, and 3). each register bank has eight 4-bit registers and paired 4-bit registers are 8-bit addressable. register a is used as a 4-bit accumulator and register pair ea as an 8-bit extended accumulator. the carry flag bit can also be used as a 1-bit accumulator. register pairs wx, wl, and hl are used as address pointers for indirect addressing. to limit the possibility of data corruption due to incorrect register addressing, it is advisable to use register bank 0 for the main program and banks 1, 2, and 3 for interrupt service routines.
s3p7588x address spaces 2- 9 table 2-2. data memory organization and addressing addresses register areas bank emb value smb value 000h?01fh working registers 0 0, 1 0 020h?0ffh stack and general-purpose registers 100h?1ffh general-purpose registers 1 1 1 200h?2ffh general-purpose registers 2 1 2 f80h?fffh peripheral hardware registers 15 0, 1 15 f f programming tip ? clearing data memory banks 0 and 1 clear banks 0 and 1 of the data memory area: ramclr smb 1 ; ram (100h?1ffh) clear ld hl,#00h ld a,#0h rmcl1 ld @hl,a incs hl jr rmcl1 smb 0 ; ram (010h?0ffh) clear ld hl,#10h rmcl0 ld @hl,a incs hl jr rmcl0
address spaces s3p7 588x 2- 10 working registers working registers, mapped to ram address 000h?01fh in data memory bank 0, are used to temporarily store intermediate results during program execution, as well as pointer values used for indirect addressing. unused registers may be used as general-purpose memory. working register data can be manipulated as 1-bit units, 4-bit units or, using paired registers, as 8-bit units. working register bank 0 register bank 1 000h a e l h x w z y a ... y a ... y a ... y register bank 2 register bank 3 0001 002h 003h 004h 005h 006h 007h 008h 00fh 010h 017h 018h 01fh data memory bank 0 figure 2-4. working register map
s3p7588x address spaces 2- 11 working register banks for addressing purposes, the working register area is divided into four register banks ? bank 0, bank 1, bank 2, and bank 3. any one of these banks can be selected as the working register bank by the register bank selection instruction (srb n) and by setting the status of the register bank enable flag (erb). generally, working register bank 0 is used for the main program, and banks 1, 2, and 3 for interrupt service routines. following this convention helps to prevent possible data corruption during program execution due to contention in register bank addressing. table 2-3. working register organization and addressing erb setting srb settings selected register bank 3 2 1 0 0 0 0 x x always set to bank 0 0 0 bank 0 1 0 0 0 1 bank 1 1 0 bank 2 1 1 bank 3 note: x = not applicable. paired working registers each of the register banks is subdivided into eight 4-bit registers. these registers, named y, z, w, x, h, l, e and a, can either be manipulated individually using 4-bit instructions, or together as register pairs for 8-bit data manipulation. the names of the 8-bit register pairs in each register bank are ea, hl, wx, yz and wl. registers a, l, x and z always become the lower nibble when registers are addressed as 8-bit pairs. this makes a total of eight 4-bit registers or four 8-bit double registers in each of the four working register banks. y z w x h l e a (msb) (lsb) (msb) (lsb) figure 2-5. register pair configuration
address spaces s3p7 588x 2- 12 special-purpose working registers register a is used as a 4-bit accumulator and double register ea as an 8-bit accumulator. the carry flag can also be used as a 1-bit accumulator. 8-bit double registers wx, wl and hl are used as data pointers for indirect addressing. when the hl register serves as a data pointer, the instructions ldi, ldd, xchi, and xchd can make very efficient use of working registers as program loop counters by letting you transfer a value to the l register and increment or decrement it using a single instruction. c a ea 1-bit accumulator 4-bit accumulator 8-bit accumulator figure 2-6. 1-bit, 4-bit, and 8-bit accumulator recommendation for multiple interrupt processing if more than four interrupts are being processed at one time, you can avoid possible loss of working register data by using the push rr instruction to save register contents to the stack before the service routines are executed in the same register bank. when the routines have executed successfully, you can restore the register contents from the stack to working memory using the pop instruction.
s3p7588x address spaces 2- 13 f f programming tip ? selecting the working register area the following examples show the correct programming method for selecting working register area: 1. when erb = "0": vent2 1,0,int0 ; emb ? 1, erb ? 0, jump to int0 address ; int0 push sb ; push current smb, srb srb 2 ; instruct ion does not execute because erb = "0" push hl ; push hl register contents to stack push wx ; push wx register contents to stack push yz ; push yz register contents to stack push ea ; push ea register contents to stack smb 0 ld ea,#00h ld 80h,ea ld hl,#40h incs hl ld wx,ea ld yz,ea pop ea ; pop ea register contents from stack pop yz ; pop yz register contents from stack pop wx ; pop wx register contents from stack pop hl ; pop hl register contents from stack pop sb ; pop current smb, srb iret the pop instructions execute alternately with the push instructions. if an smb n instruction is used in an interrupt service routine, a push and pop sb instruction must be used to store and restore the current smb and srb values, as shown in example 2 below. 2. when erb = "1": vent2 1,1,int0 ; emb ? 1, erb ? 1, jump to int0 address ; int0 push sb ; store current smb, srb srb 2 ; select register bank 2 because of erb = "1" smb 0 ld ea,#00h ld 80h,ea ld hl,#40h incs hl ld wx,ea ld yz,ea pop sb ; restore smb, srb iret
address spaces s3p7 588x 2- 14 f f programming tip ? selecting the working register area the following examples show the correct programming method for selecting working register area: 1. when erb = "0": vent2 1,0,int0 ; emb ? 1, erb ? 0, jump to int0 address int0 push sb ; push current smb, srb srb 2 ; instruction does not execute because erb = "0" push hl ; push hl register contents to stack push wx ; push wx register contents to stack push yz ; push yz register contents to stack push ea ; push ea register contents to stack smb 0 ld ea,#00h ld 80h,ea ld hl,#40h incs hl| ld wx,ea ld yz,ea pop ea ; pop ea register contents from stack pop yz ; pop yz register contents from stack pop wx ; pop wx register contents from stack pop hl ; pop hl register contents from stack pop sb ; pop current smb, srb iret the pop instructions execute alternately with the push instructions. if an smb n instruction is used in an interrupt service routine, a push and pop sb instruction must be used to store and restore the current smb and srb values, as shown in example 2 below. 2. when erb = "1": vent2 1,1,int0 ; emb ? 1, erb ? 1, jump to int0 address int0 push sb ; store current smb, srb srb 2 ; select register bank 2 because of erb = "1" smb 0 ld ea,#00h ld 80h,ea ld hl,#40h incs hl ld wx,ea ld yz,e a pop sb ; restore smb, srb iret
s3p7588x address spaces 2- 15 stack operations stack pointer (sp) the stack pointer (sp) is an 8-bit register that stores the address used to access the stack, an area of data memory set aside for temporary storage of stack addresses. the sp can be read or written by 8 -bit control instructions. when addressing the sp, bit 0 must always remain cleared to logic zero. f80h sp3 sp2 sp1 "0" f81h sp7 sp6 sp5 sp4 there are two basic stack operations: writing to the top of the stack (push), and reading from the top of the stack (pop). a push decrements the sp and a pop increments it so that the sp always points to the top address of the last data to be written to the stack. the program counter contents and program status word are stored in the stack area prior to the execution of a call or a push instruction, or during interrupt service routines. stack operation is a lifo (last in-first out) type. the stack area is located in general-purpose data memory bank 0. during an interrupt or a subroutine, the pc value and the psw are saved to the stack area. when the routine has completed, the stack pointer is referenced to restore the pc and psw, and the next instruction is executed. the sp can address stack registers in bank 0 (addresses 000h-0ffh) regardless of the current value of the enable memory bank (emb) flag and the select memory bank (smb) flag. although general-purpose register areas can be used for stack operations, be careful to avoid data loss due to simultaneous use of the same register(s). since the reset value of the stack pointer is not defined in firmware, we recommend that you initialize the stack pointer by program code to location 00h. this sets the first register of the stack area to 0ffh. note a subroutine call occupies six nibbles in the stack; an interrupt requires six. when subroutine nesting or interrupt routines are used continuously, the stack area should be set in accordance with the maximum number of subroutine levels. to do this, estimate the number of nibbles that will be used for the subroutines or interrupts and set the stack area correspondingly. f f p rogramming tip ? initializing the stack pointer to initialize the stack pointer (sp): 1. when emb = "1": smb 15 ; select memory bank 15 ld ea,#00h ; bit 0 of accumulator a is always cleared to "0" ld sp,ea ; stack area initial address (0ffh) ? (sp) ? 1 2. when emb = "0": ld e a,#00h ld sp,ea ; memory addressing area (00h?7fh, f80h?fffh)
address spaces s3p7 588x 2- 16 push operations three kinds of push operations reference the stack pointer (sp) to write data from the source register to the stack: push instructions, call instructions, and interrupts. in each case, the sp is decreased by a number determined by the type of push operation and then points to the next available stack location. push instructions a push instruction references the sp to write two 4-bit data nibbles to the stack. two 4-bit stack addresses are referenced by the stack pointer: one for the upper register value and another for the lower register. after the push has executed, the sp is decreased by two and points to the next available stack location. call instructions when a subroutine call is issued, the call instruction references the sp to write the pc's contents to six 4 -bit stack locations. current values for the enable memory bank (emb) flag and the enable register bank (erb) flag are also pushed to the stack. since six 4-bit stack locations are used per call, you may nest subroutine calls up to the number of levels permitted in the stack. interrupt routines an interrupt routine references the sp to push the contents of the pc and the program status word (psw) to the stack. six 4-bit stack locations are used to store this data. after the interrupt has executed, the sp is decreased by six and points to the next available stack location. during an interrupt sequence, subroutines may be nested up to the number of levels which are permitted in the stack area. push (after push, sp <-- sp - 2) lower register upper register pc11 ~ pc8 pc12 pc3 ~ pc0 pc7 ~ pc4 0 0 0 erb 0 0 emb 0 0 0 0 sp - 6 sp - 5 sp - 4 sp - 3 sp - 2 sp - 1 sp pc11 ~ pc8 pc12 pc3 ~ pc0 pc7 ~ pc4 0 0 0 erb is1 is0 emb sc0 c sc2 sc1 sp - 6 sp - 5 sp - 4 sp - 3 sp - 2 sp - 1 sp sp - 2 sp - 1 sp call (after call, sp <-- sp - 6) interrupt (when int is acknowledged, sp <-- sp - 6 ) psw psw figure 2-7. push-type stack operations
s3p7588x address spaces 2- 17 pop operations for each push operation there is a corresponding pop operation to write data from the stack back to the source register or registers: for the push instruction it is the pop instruction; for call, the instruction ret or sret; for interrupts, the instruction iret. when a pop operation occurs, the sp is incremented by a number determined by the type of operation and points to the next free stack location. pop instructions a pop instruction references the sp to write data stored in two 4-bit stack locations back to the register pairs and sb register. the value of the lower 4-bit register is popped first, followed by the value of the upper 4-bit register. after the pop has executed, the sp is incremented by two and points to the next free stack location. ret and sret instructions the end of a subroutine call is signaled by the return instruction, ret or sret. the ret or sret uses the sp to reference the six 4-bit stack locations used for the call and to write this data back to the pc, the emb, and the erb. after the ret or sret has executed, the sp is incremented by six and points to the next free stack location. iret instructions the end of an interrupt sequence is signaled by the instruction iret. iret references the sp to locate the six 4- bit stack addresses used for the interrupt and to write this data back to the pc and the psw. after the iret has executed, the sp is incremented by six and points to the next free stack location. pop (sp <-- sp + 2) lower register upper register pc11 ~ pc8 pc12 pc3 ~ pc0 pc7 ~ pc4 0 0 0 erb 0 0 emb 0 0 0 0 sp + 5 sp + 4 sp + 3 sp + 2 sp + 1 sp pc11 ~ pc8 pc12 pc3 ~ pc0 pc7 ~ pc4 0 0 0 erb is1 is0 emb sc0 c sc2 sc1 sp + 2 sp + 1 sp ret or sret (sp <-- sp + 6) iret (sp <-- sp + 6 ) psw sp + 6 psw sp + 5 sp + 4 sp + 3 sp + 2 sp + 1 sp sp + 6 figure 2-8. pop-type stack operations
address spaces s3p7 588x 2- 18 bit sequential carrier (bsc) the bit sequential carrier (bsc) is a 8-bit general register that can be manipulated using 1-, 4-, and 8-bit ram control instructions. resetb clears all bsc bit values to logic zero. using the bsc, you can specify sequential addresses and bit locations using 1-bit indirect addressing ( memb.@l). (bit addressing is independent of the current emb value.) this way, programs can process 8-bit data by moving the bit location sequentially and then incrementing or decreasing the value of the l register. bsc data can also be manipulated using direct addressing. if the values of the l register are 0h at bsc2.@l, the address and bit location assignment is fc2h.0. if the l register content is 8h at bsc2.@l, the address and bit location assignment is fc3h.3. table 2-4. bsc register organization name address bit 3 bit 2 bit 1 bit 0 bsc0 fc0h bsc0.3 bsc0.2 bsc0.1 bsc0.0 bsc1 fc1h bsc1.3 bsc1.2 bsc1.1 bsc1.0 bsc2 fc2h bsc2.3 bsc2.2 bsc2.1 bsc2.0 bsc3 fc3h bsc3.3 bsc3.2 bsc3.1 bsc3.0 f f programming tip ? using the bsc register to output 16-bit data to use the bit sequential carrier (bsc) register to output 8-bit data (59h) to the p2.3 pin: bits emb smb 15 ld ea,#59h ; ld bsc2,ea ; bsc2 ? a, bsc3 ? e smb 0 ld l,#8h ; agn ldb c,bsc2.@l ; ldb p2.3,c ; p2.3 ? c incs l jr agn ret
s3p7588x address spaces 2- 19 program counter (pc) a 13-bit program counter (pc) stores addresses for instruction fetches during program execution. whenever a reset operation or an interrupt occurs, bits pc12 through pc0 are set to the vector address. usually, the pc is incremented by the number of bytes of the instruction being fetched. one exception is the 1- byte ref instruction which is used to reference instructions stored in the rom. program status word (psw) the program status word (psw) is an 8-bit word that defines system status and program execution status and which permits an interrupted process to resume operation after an interrupt request has been serviced. psw values are mapped as follows: fb0h is1 is0 emb erb fb1h c sc2 sc1 sc0 the psw can be manipulated by 1-bit or 4-bit read/write and by 8-bit read instructions, depending on the specific bit or bits being addressed. the psw can be addressed during program execution regardless of the current value of the enable memory bank (emb) flag. part or all of the psw is saved to stack prior to execution of a subroutine call or hardware interrupt. after the interrupt has been processed, the psw values are popped from the stack back to the psw address. when a resetb is generated, the emb and erb values are set according to the resetb vector address, and the carry flag is left undefined (or the current value is retained). psw bits is0, is1, sc0, sc1, and sc2 are all cleared to logical zero. table 2-5. program status word bit descriptions psw bit identifier description bit addressing read/write is1, is0 interrupt status flags 1, 4 r/w emb enable memory bank flag 1 r/w erb enable register bank flag 1 r/w c carry flag 1 r/w sc2, sc1, sc0 program skip flags 8 r
address spaces s3p7 588x 2- 20 interrupt status flags (is0, is1) psw bits is0 and is1 contain the current interrupt execution status values. you can manipulate is0 and is1 flags directly using 1-bit ram control instructions by manipulating interrupt status flags in conjunction with the interrupt priority register (ipr), you can process multiple interrupts by anticipating the next interrupt in an execution sequence. the interrupt priority control circuit determines the is0 and is1 settings in order to control multiple interrupt processing. when both interrupt status flags are set to "0", all interrupts are allowed. the priority with which interrupts are processed is then determined by the ipr. when an interrupt occurs, is0 and is1 are pushed to the stack as part of the psw and are automatically incremented to the next status. then, when the interrupt service routine ends with an iret instruction, is0 and is1 values are restored to the psw. table 2-6 shows the effects of is0 and is1 flag settings. table 2-6. interrupt status flag bit settings is1 value is0 value status of currently executing process effect of is0 and is1 settings on interrupt request control 0 0 0 all interrupt requests are serviced 0 1 1 only high-priority interrupt as determined in the interrupt priority register (ipr) is serviced 1 0 2 no more interrupt requests are serviced 1 1 ? not applicable; these bit settings are undefined since interrupt status flags can be addressed by write instructions, programs can exert direct control over interrupt processing status. before interrupt status flags can be addressed, however, you must first execute a di instruction to inhibit additional interrupt routines. when the bit manipulation has been completed, execute an ei instruction to re -enable interrupt processing. f f programming tip ? setting isx flags for interrupt processing the following instruction sequence shows how to use the is0 and is1 flags to control interrupt processing: intb di ; disable interrupt bitr is1 ; is1 ? 0 bits is0 ; allow interrupts according to ipr priority level ei ; enable interrupt
s3p7588x address spaces 2- 21 emb flag (emb) the emb flag is used to enable whether the memory bank selected by smb register is to be valid or not. in this way, it controls the addressing mode for data memory banks 0, 1, or 15. when the emb flag is "0", the data memory address space is restricted to bank 15 and addresses 000h?07fh of memory bank 0, regardless of the smb register contents. when the emb flag is set to "1", the general-purpose areas of bank 0, 1, and 15 can be accessed by using the appropriate smb value. f f programming tip ? using the emb flag to select memory banks emb flag settings for memory bank selection: 1. when emb = "0": smb 1 ; non-essential instruction since emb = "0" ld a,#9h ld 90h,a ; (f90h) ? a, bank 15 is selected ld 34h,a ; (034h) ? a, bank 0 is selected smb 0 ; non-essential instruction since emb = "0" ld 90h,a ; (f90h) ? a, bank 15 is selected ld 34h,a ; (034h) ? a, bank 0 is selected smb 15 ; non-essential instruction, since emb = "0" ld 20h,a ; (020h) ? a, bank 0 is selected ld 90h,a ; (f90h) ? a, bank 15 is selected 2. when emb = "1": smb 1 ; select memory bank 1 ld a,#9h ld 90h,a ; (190h) ? a, bank 1 is selected ld 34h,a ; (134h) ? a, bank 1 is selected smb 0 ; select memory bank 0 ld 90h,a ; (090h) ? a, bank 0 is selected ld 34h,a ; (034h) ? a, bank 0 is selected smb 15 ; select memory bank 15 ld 20h,a ; program error, but assembler does not detect it ld 90h,a ; (f90h) ? a, bank 15 is selected
address spaces s3p7 588x 2- 22 erb flag (erb) the 1-bit register bank enable flag (erb) determines the range of addressable working register area. when the erb flag is "1", the working register area from register banks 0 to 3 is selected according to the register bank selection register (srb). when the erb flag is "0", register bank 0 is the selected working register area, regardless of the current value of the register bank selection register (srb). when an internal resetb is generated, bit 6 of program memory address 0000h is written to the erb flag. this automatically initializes the flag. when a vectored interrupt is generated, bit 6 of the respective address table in program memory is written to the erb flag, setting the correct flag status before the interrupt service routine is executed. during the interrupt routine, the erb value is automatically pushed to the stack area along with the other psw bits. afterwards, it is popped back to the fb0h.0 bit location in the psw. the initial erb flag settings for each vectored interrupt are defined using ventn instructions. f f programming tip ? using the erb flag to select register banks erb flag settings for register bank selection: 1. when erb = "0": srb 1 ; register bank 0 is selected (since erb = "0", t he ; srb is configured to bank 0) ld ea,#34h ; bank 0 ea ? #34h ld hl,ea ; bank 0 hl ? ea srb 2 ; register bank 0 is selected ld yz,ea ; bank 0 yz ? ea srb 3 ; register bank 0 is selected ld wx,ea ; bank 0 wx ? ea 2. when erb = "1": srb 1 ; register bank 1 is selected ld ea,#34h ; bank 1 ea ? #34h ld hl,ea ; bank 1 hl ? bank 1 ea srb 2 ; register bank 2 is selected ld yz,ea ; bank 2 yz ? bank2 ea srb 3 ; register bank 3 is selected ld wx,ea ; bank 3 wx ? bank 3 ea
s3p7588x address spaces 2- 23 skip condition flags (sc2, sc1, sc0) the skip condition flags sc2, sc1, and sc0 indicate the current program skip conditions and are set and reset automatically during program execution. skip condition flags can only be addressed by 8-bit read instructions. direct manipulation of the sc2, sc1, and sc0 bits is not allowed. carry flag (c) the carry flag is used to save the result of an overflow or borrow when executing arithmetic instructions involving a carry (adc, sbc). the carry flag can also be used as a 1-bit accumulator for performing boolean operations involving bit-addressed data memory. if an overflow or borrow condition occurs when executing arithmetic instructions with carry (adc, sbc), the carry flag is set to "1". otherwise, its value is "0". when a resetb occurs, the current value of the carry flag is retained during power-down mode, but when normal operating mode resumes, its value is undefined. the carry flag can be directly manipulated by predefined set of 1-bit read/write instructions, independent of other bits in the psw. only the adc and sbc instructions, and the instructions listed in table 2-7, affect the carry flag. table 2-7. valid carry flag manipulation instructions operation type instructions carry flag manipulation direct manipulation scf set carry flag to "1" rcf clear carry flag to "0" (reset carry flag) ccf invert carry flag value (complement carry flag) btst c test carry and skip if c = "1" bit transfer ldb c (operand) (note 1) load carry flag value to the specified bit ldb c, (operand) (note 1) load contents of the specified bit to carry flag data transfer rrc a rotate right through carry flag boolean manipulation band c, (operand) (note 1) and the specified bit with contents of carry flag and save the result to the carry flag bor c, (operand) (note 1) or the specified bit with contents of carry flag and save the result to the carry flag bxor c, (operand) (note 1) xor the specified bit with contents of carry flag and save the result to the carry flag interrupt routine intn (note 2) save carry flag to stack with other psw bits return from interrupt iret restore carry flag from stack with other psw bits notes: 1. the operand has three bit addressing formats: mema.a, memb.@l, and @h + da.b. 2. ' intn' refers to the specific interrupt being executed and is not an instruction.
address spaces s3p7 588x 2- 24 f f programming tip ? using the carry flag as a 1-bit accumulator 1. set the carry flag to logic one: scf ; c ? 1 ld ea,#0c3h ; ea ? #0c3h ld hl,#0aah ; hl ? #0aah adc ea,hl ; ea ? #0c3h + #0aah + #1h, c ? 1 2. logical-and bit 3 of address 3fh with p3.3 and output the result to p5.0: ld h,#3h ; set the upper four bits of the address to the h register value ldb c,@h+0fh.3 ; c ? bit 3 of 3fh band c,p3.3 ; c ? c and p3.3 ldb p5.0,c ; output result from carry flag to p5.0
s3p7588x addressing modes 3- 1 3 addressing modes overview the enable memory bank flag, emb, controls the two addressing modes for data memory. when the emb flag is set to logic one, you can address the entire ram area; when the emb flag is cleared to logic zero, the addressable area in the ram is restricted to specific locations. the emb flag works in connection with the select memory bank instruction, smbn. you will recall that the smbn instruction is used to select ram bank 0, 1, 2 or 15. the smb setting is always contained in the upper four bits of a 12-bit ram address. for this reason, both addressing modes (emb = "0" and emb = "1") apply specifically to the memory bank indicated by the smb instruction, and any restrictions to the addressable area within banks 0, 1, 2 or 15. direct and indirect 1-bit, 4-bit, and 8-bit addressing methods can be used. several ram locations are addressable at all times, regardless of the current emb flag setting. here are a few guidelines to keep in mind regarding data memory addressing: ? when you address peripheral hardware locations in bank 15, the mnemonic for the memory-mapped hardware component can be used as the operand in place of the actual address location. ? always use an even-numbered ram add ress as the operand in 8-bit direct and indirect addressing. ? with direct addressing, use the ram address as the instruction operand; with indirect addressing, the instruction specifies a register which contains the operand's address.
addressing modes s3 p7588x 3- 2 000h 01fh 020h 0ffh 100h 1ffh 200h 2ffh notes: 1. 'x' means don't care. 2. blank columns indicate ram areas that are not addressable, given the addressing method and enable memory bank (emb) flag setting shown in the column headers. 07fh 080h bank 15 (peripheral hardware registers) f80h fffh fb0h fbfh fc0h da da.b emb = 0 emb = 1 @hl @h + da.b emb = 0 emb = 1 @wx @wl x x mema.b x memb.@l addressing mode ram areas working registers bank 0 (general registers and stack) bank 1 (general registers) bank 2 (general registers) smb = 0 smb = 0 smb = 1 smb = 1 smb = 2 smb = 2 smb = 15 smb = 15 figure 3-1. ram address structure
s3p7588x addressing modes 3- 3 emb and erb initialization values the emb and erb flag bits are set automatically by the values of the reset vector address and the interrupt vector address. when a reset is generated internally, bit 7 of program memory address 0000h is written to the emb flag, initializing it automatically. when a vectored interrupt is generated, bit 7 of the respective vector address table is written to the emb. this automatically sets the emb flag status for the interrupt service routine. when the interrupt is serviced, the emb value is automatically saved to stack and then restored when the interrupt routine has completed. at the beginning of a program, the initial emb and erb flag values for each vectored interrupt must be set by using vent instruction. the emb and erb can be set or reset by bit manipulation instructions (bits, bitr) despite the current smb setting. f f programming tip ? initializing the emb and erb flags the following assembly instructions show how to initialize the emb and erb flag settings: org 0000h ; rom address assignment vent0 1,0,reset ; e mb ? 1, erb ? 0, branch reset vent1 0,1,intb ; emb ? 0, erb ? 1, branch intb vent2 0,1,int0 ; emb ? 0, erb ? 1, branch int0 vent3 0,1,int1 ; emb ? 0, erb ? 1, branch int1 nop nop vent5 0,1,intt0 ; emb ? 0, erb ? 1, branch intt0 vent6 0,1,intt1 ; emb ? 0, erb ? 1, branch intt1 reset bitr emb
addressing modes s3 p7588x 3- 4 enable memory bank settings emb = "1" when the enable memory bank flag emb is set to logic one, you can address the data memory bank specified by the select memory bank (smb) value (0, 1, 2 or 15) using 1-, 4-, or 8-bit instructions. you can use both direct and indirect addressing modes. the addressable ram areas when emb = "1" are as follows: ? if smb = 0, 000h?0ffh ? if smb = 1, 100h?1ffh ? if smb = 2, 200h?2ffh ? if smb = 15, f80h?fffh emb = "0" when the enable memory bank flag emb is set to logic zero, the addressable area is defined independently of the smb value, and is restricted to specific locations depending on whether a direct or indirect address mode is used. if emb = "0", the addressable area is restricted to locations 000h?07fh in bank 0 and to locations f80h?fffh in bank 15 for direct addressing. for indirect addressing, only locations 000h?0ffh in bank 0 are addressable, regardless of smb value. to address the peripheral hardware register (bank 15) using indirect addressing, the emb flag must first be set to "1" and the smb value to "15". when a reset occurs, the emb flag is set to the value contained in bit 7 of rom address 0000h. emb-independent addressing at any time, several areas of the data memory can be addressed independently of the current status of the emb flag. these exceptions are described in table 3-1. table 3-1. ram addressing not affected by the emb value address addressing method affected hardware program examples 000h?0ffh 4-bit indirect addressing using wx and wl register pairs; 8-bit indirect addressing using sp not applicable ld a,@wx push pop fb0h?fbfh ff0h?fffh 1-bit direct addressing psw, iex, irqx, i/o bits emb bitr ie4 fc0h?fffh 1-bit indirect addressing using the l r egister i/o band c,p3.@l
s3p7588x addressing modes 3- 5 select bank register (sb) the select bank register (sb) is used to assign the memory bank and register bank. the 8-bit sb register consists of the 4-bit select register bank register (srb) and the 4-bit select memory bank register (smb), as shown in figure 3-2. during interrupts and subroutine calls, sb register contents can be saved to stack in 8-bit units by the push sb instruction. you later restore the value to the sb using the pop sb instruction. smb 3 smb 2 smb 1 smb 0 0 0 srb 0 srb 0 srb (f82h) smb (f83h) sb register figure 3-2. smb and srb values in the sb register select register bank (srb) instruction the select register bank (srb) value specifies which register bank is to be used as a working register bank. the srb value is set by the 'srb n' instruction, where n = 0, 1, 2, 3. one of the four register banks is selected by the combination of erb flag status and the srb value that is set using the 'srb n' instruction. the current srb value is retained until another register is requested by program software. push sb and pop sb instructions are used to save and restore the contents of srb during interrupts and subroutine calls. reset clears the 4-bit srb value to logic zero. select memory bank (smb) instruction to select one of the four available data memory banks, you must execute an smb n instruction specifying the number of the memory bank you want (0, 1, 2 or 15). for example, the instruction 'smb 1' selects bank 1 and 'smb 15' selects bank 15. (and remember to enable the selected memory bank by making the appropriate emb flag setting. the upper four bits of the 12-bit data memory address are stored in the smb register. if the smb value is not specified by software (or if a reset does not occur) the current value is retained. reset clears the 4-bit smb value to logic zero. the push sb and pop sb instructions save and restore the contents of the smb register to and from the stack area during interrupts and subroutine calls.
addressing modes s3 p7588x 3- 6 direct and indirect addressing 1-bit, 4-bit, and 8-bit data stored in data memory locations can be addressed directly using a specific register or bit address as the instruction operand. indirect addressing specifies a memory location that contains the required direct address. the ks57 instruction set supports 1-bit, 4-bit, and 8 -bit indirect addressing. for 8-bit indirect addressing, an even-numbered ram address must always be used as the instruction operand. 1-bit addressing table 3-2. 1-bit direct and indirect ram addressing operand notation addressing mode description emb flag setting addressable area memory bank hardware i/o mapping da.b direct: bit is indicated by the 0 000h?07fh bank 0 ? ram address (da), memory bank selection, and specified bit number (b). f80h?fffh bank 15 all 1-bit addressable peripherals (smb = 15) 1 000h?fffh smb = 0, 1, 2, 15 mema.b direct: bit is indicated by addressable area ( mema) and bit number (b). x fb0h?fbfh ff0h?fffh bank 15 is0, is1, emb, erb, iex, irqx, pn.n memb.@l indirect: lower two bits of register l as indicated by the upper 10 bits of ram area ( memb) and the upper two bits of register l. x fc0h?fffh bank 15 pn.n @h + da.b indirect: bit indicated by the lower four bits of the address (da), memory bank selection, and the h register identifier. 0 000h?0ffh bank 0 all 1-bit addressable peripherals (smb = 15) 1 000h?fffh smb = 0, 1, 2, 15 note : x = not applicable.
s3p7588x addressing modes 3- 7 f f programming tip ? 1-bit addressing modes 1-bit direct addressing 1. if emb = "0": aflag equ 34h.3 bflag equ 85h.3 cflag equ 0bah.0 smb 0 bits aflag ; 34h.3 ? 1 bits bflag ; f85h.3 (bmod.3) ? 1 btst cflag ; if fbah.0 (irqw) = 1, skip bits bflag ; else if, fbah.0 (irqw) = 0, f85h.3 (bmod.3) ? 1 bits p3.0 ; ff3h.0 (p3.0) ? 1 2. if emb = "1": aflag equ 34h.3 bflag equ 85h.3 cflag equ 0bah.0 smb 0 bits aflag ; 34h.3 ? 1 bits bflag ; 85h.3 ? 1 btst cflag ; if 0bah.0 = 1, skip bits bflag ; else if 0bah.0 = 0, 085h.3 ? 1 bits p3.0 ; ff3h.0 (p3.0) ? 1 1-bit indirect addressing 1. if emb = "0": aflag equ 34h.3 bflag equ 85h.3 cflag equ 0bah.0 smb 0 ld h,#0bh ; h ? #0bh btstz @h+cflag ; if 0bah.0 = 1, 0bah.0 ? 0 and skip bits cflag ; else if 0bah.0 = 0, fbah.0 (irqw) ? 1 2. if emb = "1": aflag equ 34h.3 bflag equ 85h.3 cflag equ 0bah.0 smb 0 ld h,#0bh ; h ? #0bh btstz @h+cflag ; if 0bah.0 = 1, 0bah.0 ? 0 and skip bits cflag ; else if 0bah.0 = 0, 0bah.0 ? 1
addressing modes s3 p7588x 3- 8 4-bit addressing table 3-3. 4-bit direct and indirect ram addressing operand notation addressing mode description emb flag setting addressable area memory bank hardware i/o mapping da direct: 4-bit address indicated 0 000h?07fh bank 0 ? by the ram address (da) and the memory bank selection f80h?fffh bank 15 all 4-bit addressable peripherals 1 000h?fffh smb = 0, 1, 2 15 (smb = 15) @hl indirect: 4-bit address indicated by the memory bank selection and register hl 0 000h?0ffh bank 0 ? 1 000h?fffh smb = 0, 1, 2 15 all 4-bit addressable peripherals (smb = 15) @wx indirect: 4-bit address indicated by register wx x 000h?0ffh bank 0 ? @wl indirect: 4-bit address indicated by register wl x 000h?0ffh bank 0 note : x = not applicable. f f programming tip ? 4-bit addressing modes 4-bit direct addressing 1. if e mb = "0": adata equ 46h bdata equ 8eh smb 15 ; non-essential instruction, since emb = "0" ld a,p3 ; a ? (p3) smb 0 ; non-essential instruction, since emb = "0" ld adata,a ; (046h) ? a ld bdata,a ; (f8eh) ? a 2. if emb = "1": adata equ 46h bdata equ 8eh smb 15 ld a,p3 ; a ? (p3) smb 0 ld adata,a ; (046h) ? a ld bdata,a ; (08eh) ? a
s3p7588x addressing modes 3- 9 f f programming tip ? 4-bit addressing modes (continued) 4-bit indirect addressing (example 1) 1. if emb = "0", compare bank 0 locations 040h?046h with bank 0 locations 060h?066h: adata equ 46h bdata equ 66h smb 1 ; non-essential instruction, since emb = "0" ld hl,#bdata ld wx,#adata comp ld a,@wl ; a ? bank 0 (040h?046h) cpse a,@hl ; if bank 0 (060h?066h) = a, skip sret decs l jr comp ret 2. if emb = "1", compare bank 0 loc ations 040h?046h to bank 1 locations 160h?166h: adata equ 46h bdata equ 66h smb 1 ld hl,#bdata ld wx,#adata comp ld a,@wl ; a ? bank 0 (040h?046h) cpse a,@hl ; if bank 1 (160h?166h) = a, skip sret decs l jr comp ret
addressing modes s3 p7588x 3- 10 f f programming tip ? 4-bit addressing modes (continued) 4-bit indirect addressing (example 2) 1. if emb = "0", exchange bank 0 locations 040h?046h with bank 0 locations 060h?066h: adata equ 46h bdata equ 66h smb 1 ; non-essential instruction, since emb = "0" ld hl,#bdata ld wx,#adata trans ld a,@wl ; a ? bank 0 (040h?046mh) xchd a,@hl ; bank 0 (060h?066h) ? a jr trans 2. if emb = "1", exchange bank 0 locations 040h?046h to bank 1 locations 160h?166h: adata equ 46h bdata equ 66h smb 1 ld hl,#bdata ld wx,#adata trans ld a,@wl ; a ? bank 0 (040h?046h) xchd a,@hl ; bank 1 (160h?166h) ? a jr trans
s3p7588x addressing modes 3- 11 8-bit addressing table 3-4. 8-bit direct and indirect ram addressing instructio n notation addressing mode description emb flag setting addressable area memory bank hardware i/o mapping da direct: 8-bit address indicated 0 000h?07fh bank 0 ? by the ram address ( da = even number ) and memory bank selection f80h?fffh bank 15 all 8-bit addressable peripherals 1 000h?fffh smb = 0, 1, 2, 15 (smb = 15) @hl indirect: the 8-bit address indicated by the memory bank selection and register hl; (the 4 -bit l register value must be an even number) 0 000h?0ffh bank 0 ? 1 000h?fffh smb = 0, 1, 2, 15 all 8-bit addressable peripherals (smb = 15)
addressing modes s3 p7588x 3- 12 f f programming tip ? 8-bit addressing modes 8-bit direct addressing 1. if emb = "0": adata equ 46h bdata equ 8eh smb 15 ; non-essential instruction, since emb = "0" ld ea,p4 ; e ? (p5), a ? (p4) smb 0 ld adata,ea ; (046h) ? a, (047h) ? e ld bdata,ea ; (f8eh) ? a, (f8fh) ? e 2. if emb = "1": adata equ 46h bdata equ 8eh smb 15 ld ea,p4 ; e ? (p5), a ? (p4) smb 0 ld adata,ea ; (046h) ? a, (047h) ? e ld bda ta,ea ; (08eh) ? a, (08fh) ? e 8-bit indirect addressing 1. if emb = "0": adata equ 146h smb 1 ; non-essential instruction, since emb = "0" ld hl,#adata ld ea,@hl ; a ? (046h), e ? (047h) 2. if emb = "1": adata equ 146h smb 1 ld hl,#adata ld ea,@hl ; a ? (146h), e ? (147h)
s3p7588x memory map 4- 1 4 memory map overview to support program control of peripheral hardware, i/o addresses for peripherals are memory-mapped to bank 15 of the ram. memory mapping lets you use a mnemonic as the operand of an instruction in place of the specific memory location. access to bank 15 is controlled by the select memory bank (smb) instruction and by the enable memory bank flag (emb) setting. if the emb flag is ?0?, bank 15 can be addressed using direct addressing, regardless of the current smb value. 1-bit direct and indirect addressing can be used for specific locations in bank 15, regardless of the current emb value. i/o map for hardware registers table 4-1 contains detailed information about i/o mapping for peripheral hardware in bank 15 (register locations f80h?fffh). use the i/o map as a quick-reference source when writing application programs. the i/o map gives you the following information: ? register address ? register name (mnemonic for program addressing) ? bit values (both addressable and non- manipulable) ? read-only, write-only, or read and write addressability ? 1-bit, 4-bit, or 8-bit data manipulation characteristics
memory map s3p7588x 4- 2 table 4-1. i/o map for memory bank 15 memory bank 15 addressing mode address register bit 3 bit 2 bit 1 bit 0 r/w 1-bit 4-bit 8-bit f80h sp .3 .2 .1 ?0? r/w no no yes f81h .7 .6 .5 .4 locations f82h?f84h are not mapped. f85h bmod .3 .2 .1 .0 w .3 yes no f86h bcnt r no no yes f87h f88h wmod ?0? .2 .1 ?0? (1) w no no yes f89h .7 ?0? .5 .4 locations f8ah?f8fh are not mapped. f90h tmod0 .3 .2 ?0? ?0? w .3 no yes f91h ?0? .6 .5 .4 f92h toe1 toe0 boe ?0? r/w yes yes no f93h ?0? tol1 tol0 ?0? f94h tcnt0 r no no yes f95h f96h tref0 w no no yes f97h f98h wdmod .3 .2 .1 .0 w no no yes f99h .7 .6 .5 .4 f9ah wdflag wdtcf ?0? ?0? ?0? w yes yes no locations f9bh?f9fh are not mapped. fa0h tmod1 .3 .2 ?0? ?0? w .3 no yes fa1h ?0? .6 .5 .4 locations fa2h?fa3h are not mapped. fa4h tcnt1 r no no yes fa5h locations fa6h?fa7h are not mapped. fa8h tref1 w no no yes fa9h locations faah?fafh are not mapped. fb0h psw is1 is0 emb erb r/w yes yes yes fb1h c (2) sc2 sc1 sc0 r no no fb2h ipr ime .2 .1 .0 w ime yes no
s3p7588x memory map 4- 3 table 4-1. i/o map for memory bank 15 (continued) memory bank 15 addressing mode address register bit 3 bit 2 bit 1 bit 0 r/w 1-bit 4-bit 8-bit fb3h pcon .3 .2 .1 .0 w .3, .2 yes no fb4h imod0 ?0? ?0? .1 .0 w no yes no fb5h imod1 ?0? ?0? ?0? .0 fb6h imod2 ?0? ?0? .1 .0 locations fb7h is not mapped. fb8h ie4 irq4 ieb irqb r/w yes yes no locations fb9h is not mapped. fbah ?0? ?0? iew irqw r/w yes yes no fbbh ?0? ?0? iet1 irqt1 fbch ?0? ?0? iet0 irqt0 locations fbdh is not mapped. fbeh ie1 irq1 ie0 irq0 r/w yes no no fbfh ?0? ?0? ie2 irq2 fc0h bsc0 r/w yes no yes fc1h bsc1 fc2h bsc2 fc3h bsc3 locations fc4h?fcfh are not mapped. fd0h clmod .3 ?0? .1 .0 w no yes no locations fd1h is not mapped. fd2h dtmr ?0? .2 .1 .0 w no no yes fd3h .7 .6 .5 .4 fd4h dtgr .3 .2 .1 .0 w no no yes fd5h ?0? ?0? ?0? .4 locations fd6h?fd9h are not mapped. fdah pne1 pne4.3 pne4.2 pne4.1 pne4.0 w no no yes fdbh pne5.3 pne5.2 pne5.1 pne5.0 fdch pumod1 pur1.3 pur1.2 pur1.1 pur1.0 w no no yes fddh pur5 pur4 pur3 pur2 fdeh pumod2 pur9 pur8 pur7 pur6 w no yes no locations fdfh?fe7h are not mapped. fe8h pmg1 pm2.3 pm2.2 pm2.1 pm2.0 w no no yes fe9h pm3.3 pm3.2 pm3.1 pm3.0
memory map s3p7588x 4- 4 table 4-1. i/o map for memory bank 15 (continued) memory bank 15 addressing mode address register bit 3 bit 2 bit 1 bit 0 r/w 1-bit 4-bit 8-bit feah pmg2 pm4.3 pm4.2 pm4.1 pm4.0 w no no yes febh pm5.3 pm5.2 pm5.1 pm5.0 fech pmg3 pm6.3 pm6.2 pm6.1 pm6.0 fedh pm7.3 pm7.2 pm7.1 pm7.0 feeh pmg4 pm8.3 pm8.2 pm8.1 pm8.0 w no no yes fefh ?0? pm9.2 pm9.1 pm9.0 locations ff0h is not mapped. ff1h port 1 .3 .2 .1 .0 r yes yes no ff2h port 2 .3 .2 .1 .0 r/w yes yes yes ff3h port 3 .3 / .7 .2 / .6 .1 / .5 .0 / .4 ff4h port 4 .3 .2 .1 .0 r/w yes yes yes ff5h port 5 .3 / .7 .2 / .6 .1 / .5 .0 / .4 ff6h port 6 .3 .2 .1 .0 r/w yes yes yes ff7h port 7 .3 / .7 .2 / .6 .1 / .5 .0 / .4 ff8h port 8 .3 .2 .1 .0 r/w yes yes yes ff9h port 9 ?0? .2 / .6 .1 / .5 .0 / .4 notes: 1. bit 0 in the wmod register must be set to logic ?0? 2. the carry flag can be read or written by specific bit manipulation instructions only. register descriptions in this section, register descriptions are presented in a consistent format to familiarize you with the memory- mapped i/o locations in bank 15 of the ram. figure 4-1 describes features of the register description format. register descriptions are arranged in alphabetical order. programmers can use this section as a quick-reference source when writing application programs. counter registers, buffer registers, and reference registers, as well as the stack pointer and port i/o latches, are not included in these descriptions. more detailed information about how these registers are used is included in part ii of this manual, ?hardware descriptions,? in the context of the corresponding peripheral hardware module descriptions.
s3p7588x memory map 4- 5 clmod - clock output mode control register fb2h bit identifier reset value read/write bit addressing w 4 0 3 .3 register id register name register location in ram bank 15 bit number in msb to lsb order bit identifier used for bit addressing bit value immediately following a reset type of addressing that must be used to address the bit (1-bit, 4-bit, or 8-bit) r = read-only w = write-only r/w = read/write register and bit ids used for bit addressing description of the effect of specific bit settings name of individual bit or related bits w 0 2 .2 4 w 0 1 .1 4 w 0 0 .0 4 clmod.2 clmod.1 -.0 associated hardware module cpu bit 2 0 always logic zero enable/disable clock output control bit 0 1 disable interrupt processing globally enable interrupt processing globally clock source and frequency selection control bits select cpu clock source select system clock fxx/8 (524khz at 4.19mhz) 0 0 1 1 0 1 0 1 select system clock fxx/64 (65.5khz at 4.19mhz) select system clock fxx/16 (262khz at 4.19mhz) clmod.3 figure 4-1. register description format
memory map s3p7588x 4- 6 bmod ? basic timer mode register bt f85h bit 3 2 1 0 identifier .3 .2 .1 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 1/4 4 4 4 bmod.3 basic timer restart bit 1 restart basic timer, then clear irqb flag, bcnt and bmod.3 to logic zero bmod.2 ? .0 input clock frequency and signal stabilization interval control bits 0 0 0 input clock frequency: signal stabilization interval: fx / 2 12 (1.02khz) 2 20 / fx (250ms) 0 1 1 input clock frequency: signal stabilization interval: fx / 2 9 (8.18khz) 2 17 / fx (31.3ms) 1 0 1 input clock frequency: signal stabilization interval: fx / 2 7 (32.7khz) 2 15 / fx (7.82ms) 1 1 1 input clock frequency: signal stabilization interval: fx / 2 5 (131khz) 2 13 / fx (1.95ms) notes: 1. signal stabilization interval is the time required to stabilize clock signal oscillation after stop mode is terminated by an interrupt. the stabilization interval can also be interpreted as ?interrupt interval time?. 2. when a reset occurs, the oscillation stabilization time is 31.3 ms (2 17 / fx) at 4.19mhz. 3. ? fx? is the system clock rate, given a clock frequency of 4.19mhz.
s3p7588x memory map 4- 7 clmod ? clock output mode register cpu fd0h bit 3 2 1 0 identifier .3 ?0? .1 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 clmod.3 enable/disable clock output control bit 0 disable clock output 1 enable clock output clmod.2 bit 2 0 always logic zero clmod.1 ? .0 clock source and frequency selection control bits 0 0 select cpu clock source fx/4, fx/8 or fx/64 (1.05mhz, 524khz or 65.5khz) 0 1 select system clock fx/8 (524khz) 1 0 select system clock fx/16 (262khz) 1 1 select system clock fx/64 (65.5khz) note: ? fx? is the system clock, given a clock frequency of 4.19mhz.
memory map s3p7588x 4- 8 dtmr ? dtmf mode register dtmf fd3h, fd2h bit 3 2 1 0 3 2 1 0 identifier .7 .6 .5 .4 ?0? .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 dtmr.7 ? .4 dtmr bit values for keyboard inputs 0 0 0 0 function key d 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 0 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 0 0 0 8 1 0 0 1 9 1 0 1 0 0 1 0 1 1 * 1 1 0 0 # 1 1 0 1 function key a 1 1 1 0 function key b 1 1 1 1 function key c dtmr.3 bit 3 0 always logic zero dtmr.2 ? .1 tone selection bits 0 0 dual-tone enable 1 0 dual-tone enable (alternate setting) 0 1 single-column tone enable 1 1 single-low tone enable dtmr.0 dtmf operation enable/disable bit 0 disable dtmf operation 1 enable dtmf operation
s3p7588x memory map 4- 9 dtgr ? dtmf gain register dtgr fd5h, fd4h bit 3 2 1 0 3 2 1 0 identifier ?0? ?0? ?0? .4 .3 .2 .1 .0 reset reset value 0 0 0 1 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 dtgr.4 ? .0 dtmf signal gain inputs 1 0 0 0 0 dtmf signal is amplified by 1 (default) 0 ? ? ? ? gain = .3 * 0.5 + .2 * 0.25 + .1 * 0.125 + .0 * 0.0625 1 ? ? ? 1 gain = 1.0625 + .3 * 0.5 + .2 * 0.25 + .1 * 0.125
memory map s3p7588x 4- 10 imod0 ? external interrupt 0 (int0) mode register (note) cpu b4h bit 3 2 1 0 identifier ?0? ?0? .1 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 imod0.3 ? .2 bits 3?2 0 always logic zero imod0.1 ? .0 external interrupt mode control bits 0 0 interrupt requests are triggered by a rising signal edge 0 1 interrupt requests are triggered by a falling signal edge 1 0 interrupt requests are triggered by both rising and falling signal edges 1 1 interrupt request flag ( irqx) cannot be set to logic one note: interrupt0 is dedicated for caller id interrupt.
s3p7588x memory map 4- 11 imod1 ? external interrupt 1 (int1) mode register cpu fb5h bit 3 2 1 0 identifier ?0? ?0? ?0? .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 imod1.3 ? .1 bits 3?1 0 always logic zero imod1.0 external interrupt 1 edge detection control bit 0 rising edge detection 1 falling edge detection
memory map s3p7588x 4- 12 imod2 ? external interrupt 2 (int2) mode register cpu fb6h bit 3 2 1 0 identifier ?0? ?0? .1 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 imod2.3 ? .2 bits 3?2 0 always logic zero imod2.1 ? .0 external interrupt 2 edge detection selection bit 0 0 interrupt request at int2 pin triggered by rising edge 0 1 interrupt request at ks4?ks7 triggered by falling edge 1 0 interrupt request at ks2?ks7 triggered by falling edge 1 1 interrupt request at ks0?ks7 triggered by falling edge
s3p7588x memory map 4- 13 ie0, 1, irq0, 1 ? int0, 1 interrupt enable/request flags cpu fbeh bit 3 2 1 0 identifier ie1 irq1 ie0 irq0 reset reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 ie1 int1 interrupt enable flag 0 disable interrupt requests at the int1 pin 1 enable interrupt requests at the int1 pin irq1 int1 interrupt request flag ? generate int1 interrupt (this bit is set and cleared by hardware when rising or falling edge detected at int1 pin.) ie0 int0 interrupt enable flag 0 disable interrupt requests at the int0 pin 1 enable interrupt requests at the int0 pin irq0 int0 interrupt request flag ? generate int0 interrupt (this bit is set and cleared automatically by hardware when rising or falling edge detected at int0 pin.) note: interrupt0 is dedicated for caller id interrupt.
memory map s3p7588x 4- 14 ie2, irq2 ? int2 interrupt enable/request flags cpu fbfh bit 3 2 1 0 identifier ?0? ?0? ie2 irq2 reset reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 .3 ? .2 bits 3?2 0 always logic zero ie2 int2 interrupt enable flag 0 disable int2 interrupt requests at the int2 pin (note) or ks0?ks7 pins 1 enable int2 interrupt requests at the int2 pin (note) or ks0?ks7 pins irq2 int2 interrupt request flag ? generate int2 quasi-interrupt (this bit is set and is not cleared automatically by hardware when a rising edge is detected at int2 pin (note) or when a falling edge is detected at one of the ks0?ks7 pins. since int2 is a quasi-interrupt, irq2 flag must be cleared by software.)
s3p7588x memory map 4- 15 ie4, irq4 ? int4 interrupt enable/request flags cpu fb8h ieb, irqb ? intb interrupt enable/request flags cpu fb8h bit 3 2 1 0 identifier ie4 irq4 ieb irqb reset reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 ie4 int4 interrupt enable flag 0 disable interrupt requests at the int4 pin 1 enable interrupt requests at the int4 pin irq4 int4 interrupt request flag ? generate int4 interrupt (this bit is set and cleared automatically by hardware when rising and falling signal edge detected at int4 pin.) ieb intb interrupt enable flag 0 disable intb interrupt requests 1 enable intb interrupt requests irqb intb interrupt request flag ? generate intb interrupt (this bit is set and cleared automatically by hardware when reference interval signal received from basic timer.)
memory map s3p7588x 4- 16 iet0, irqt0 ? intt0 interrupt enable/request flags cpu fbch bit 3 2 1 0 identifier ?0? ?0? iet0 irqt0 reset reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 .3 ? .2 bits 3?2 0 always logic zero iet0 intt0 interrupt enable flag 0 disable intt0 interrupt requests 1 enable intt0 interrupt requests irqt0 intt0 interrupt request flag ? generate intt0 interrupt (this bit is set and cleared automatically by hardware when contents of tcnt0 and tref0 registers match.)
s3p7588x memory map 4- 17 iet1, irqt1 ? intt1 interrupt enable/request flags cpu fbbh bit 3 2 1 0 identifier ?0? ?0? iet1 irqt1 reset reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 .2 ? .3 bits 2?3 0 always logic 0 iet1 intt1 interrupt enable flag 0 disable intt1 interrupt requests 1 enable intt1 interrupt requests irqt1 intt1 interrupt request flag ? generate intt1 interrupt (this bit is set and cleared automatically by hardware when contents of tcnt1 and tref1 registers match.)
memory map s3p7588x 4- 18 iew, irqw ? intw interrupt enable/request flags cpu fbah bit 3 2 1 0 identifier ?0? ?0? iew irqw reset reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 .3 ? .2 bits 3?2 0 always logic zero iew intw interrupt enable flag 0 disable intw interrupt requests 1 enable intw interrupt requests irqw intw interrupt request flag ? generate intw interrupt (this bit is set when the timer interval is set to 0.5 seconds or 3.19 milliseconds at the watch timer frequency of 32.768khz.) note: since intw is a quasi-interrupt, the irqw flag must be cleared by software.
s3p7588x memory map 4- 19 ipr ? interrupt priority register cpu fb2h bit 3 2 1 0 identifier ime .2 .1 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 1/4 4 4 4 ime interrupt master enable bit (msb) 0 disable all interrupt processing 1 enable processing of all interrupt service requests ipr.2 ? .0 interrupt priority assignment bits 0 0 0 normal interrupt processing according to default priority settings 0 0 1 process intb and int4 (note) interrupts at highest priority 0 1 0 process int0 interrupts at highest priority 0 1 1 process int1 interrupts at highest priority 1 0 1 process intt0 interrupts at highest priority 1 1 0 process intt1 interrupts at highest priority note: during normal interrupt processing, interrupts are processed in the order in which they occur. if two or more interrupts occur simultaneously, the processing order is determined by the default interrupt priority settings shown below. using the ipr settings, you can select specific interrupts for high-priority processing in the event of contention. when the high-priority (ipr) interrupt has been processed, waiting i nterrupts are handled according to their default priorities. the default priorities are as follows (?1? is highest priority; ?5? is lowest priority): intb, int4 1 int0 2 int1 3 intt0 4 intt1 5
memory map s3p7588x 4- 20 pcon ? power control register cpu fb3h bit 3 2 1 0 identifier .3 .2 .1 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 1/4 1/4 4 4 pcon.3 ? .2 cpu operating mode control bits 0 0 enable normal cpu operating mode 0 1 initiate idle power-down mode 1 0 initiate stop power-down mode pcon.1 ? .0 cpu clock frequency selection bits 0 0 select fx/64 1 0 select fx/8 1 1 select fx/4 note: ? fx? is the system clock.
s3p7588x memory map 4- 21 psw ? program status word cpu fb1h, fb0h bit 7 6 5 4 3 2 1 0 identifier c sc2 sc1 sc0 is1 is0 emb erb reset reset value (1) 0 0 0 0 0 0 0 read/write r/w r r r r/w r/w r/w r/w bit addressing (2) 8 8 8 1/4 1/4 1 1 c carry flag 0 no overflow or borrow condition exists 1 an overflow or borrow condition does exist sc2 ? sc0 skip condition flags 0 no skip condition exists; no direct manipulation of these bits is allowed 1 a skip condition exists; no direct manipulation of these bits is allowed is1, is0 interrupt status flags 0 0 service all interrupt requests 0 1 service only the high-priority interrupt(s) as determined in the interrupt priority register (ipr) 1 0 do not service any more interrupt requests 1 1 undefined emb enable data memory bank flag 0 restrict program access to data memory to bank 15 (f80h?fffh) and to the locations 000h?07fh in the bank 0 only 1 enable full access to data memory banks 0, 1, and 15 erb enable register bank flag 0 select register bank 0 as working register area 1 select register banks 0, 1, 2 or 3 as working register area in accordance with the select register bank (srb) instruction operand notes: 1. the value of the carry flag after a reset occurs during normal operation is undefined. if a reset occurs during power-down mode (idle or stop), the current value of the carry flag is retained. 2. the carry flag can only be addressed by a specific set of 1-bit manipulation instructions. see section 2 for detailed information.
memory map s3p7588x 4- 22 pmg1 ? port i/o mode flags ( group 1: ports 2, 3) i/o fe9h, fe8h bit 7 6 5 4 3 2 1 0 identifier pm3.3 pm3.2 ( note ) pm3.1 pm3.0 pm2.3 pm2.2 (note) pm2.1 (note) pm2.0 reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 pm3.3 p3.3 i/o mode selection flag 0 set p3.3 to input mode 1 set p3.3 to output mode pm3.2 (note) p3.2 i/o mode selection flag 0 set p3.2 to input mode 1 set p3.2 to input mode pm3.1 p3.1 i/o mode selection flag 0 set p3.1 to input mode 1 set p3.1 to output mode pm3.0 p3.0 i/o mode selection flag 0 set p3.0 to input mode 1 set p3.0 to output mode pm2.3 p2.3 i/o mode selection flag 0 set p2.3 to input mode 1 set p2.3 to output mode pm2.2 (note) p2.2 i/o mode selection flag 0 set p2.2 to input mode 1 set p2.2 to output mode pm2.1 (note) p0.1 i/o mode selection flag 0 set p2.1 to input mode 1 set p2.1 to output mode pm2.0 p2.0 i/o mode selection flag 0 set p2.0 to input mode 1 set p2.0 to output mode note: p3.2, p2.2, p2.1 is dedicated for caller id interfacing. (refer to chapter 7)
s3p7588x memory map 4- 23 pmg2 ? port i/o mode flags (group 2: ports 4, 5) i/o febh, feah bit 7 6 5 4 3 2 1 0 identifier pm5.3 pm5.2 pm5.1 pm5.0 pm4.3 pm4.2 pm4.1 pm4.0 reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 pm5.3 p5.3 i/o mode selection flag 0 set p5.3 to input mode 1 set p5.3 to output mode pm5.2 p5.2 i/o mode selection flag 0 set p5.2 to input mode 1 set p5.2 to output mode pm5.1 p5.1 i/o mode selection flag 0 set p5.1 to input mode 1 set p5.1 to output mode pm5.0 p5.0 i/o mode selection flag 0 set p5.0 to input mode 1 set p5.0 to output mode pm4.3 p4.3 i/o mode selection flag 0 set p4.3 to input mode 1 set p4.3 to output mode pm4.2 p4.2 i/o mode selection flag 0 set p4.2 to input mode 1 set p4.2 to output mode pm4.1 p4.1 i/o mode selection flag 0 set p4.1 to input mode 1 set p4.1 to output mode pm4.0 p4.0 i/o mode selection flag 0 set p4.0 to input mode 1 set p4.0 to output mode
memory map s3p7588x 4- 24 pmg3 ? port i/o mode flags (group 3: ports 6, 7) i/o fedh, fech bit 7 6 5 4 3 2 1 0 identifier pm7.3 pm7.2 pm7.1 pm7.0 pm6.3 pm6.2 pm6.1 pm6.0 reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 pm7.3 p7.3 i/o mode selection flag 0 set p7.3 to input mode 1 set p7.3 to output mode pm7.2 p7.2 i/o mode selection flag 0 set p7.2 to input mode 1 set p7.2 to output mode pm7.1 p7.1 i/o mode selection flag 0 set p7.1 to input mode 1 set p7.1 to output mode pm7.0 p7.0 i/o mode selection flag 0 set p7.0 to input mode 1 set p7.0 to output mode pm6.3 p6.3 i/o mode selection flag 0 set p6.3 to input mode 1 set p6.3 to output mode pm6.2 p6.2 i/o mode selection flag 0 set p6.2 to input mode 1 set p6.2 to output mode pm6.1 p6.1 i/o mode selection flag 0 set p6.1 to input mode 1 set p6.1 to output mode pm6.0 p6.0 i/o mode selection flag 0 set p6.0 to input mode 1 set p6.0 to output mode
s3p7588x memory map 4- 25 pmg4 ? port i/o mode flags (group 3: ports 8, 9) i/o fefh, feeh bit 7 6 5 4 3 2 1 0 identifier ?0? pm9.2 pm9.1 pm9.0 pm8.3 (note) pm8.2 (note) pm8.1 (note) pm8.0 (note) reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 .7 bit 7 0 always logic zero pm9.2 p9.2 i/o mode selection flag 0 set p9.2 to input mode 1 set p9.2 to output mode pm9.1 p9.1 i/o mode selection flag 0 set p9.1 to input mode 1 set p9.1 to output mode pm9.0 p9.0 i/o mode selection flag 0 set p 9.0 to input mode 1 set p 9.0 to output mode pm8.3 (note) p8.3 i/o mode selection flag 0 set p8.3 to input mode 1 set p8.3 to output mode pm8.2 (note) p8.2 i/o mode selection flag 0 set p8.2 to input mode 1 set p8.2 to output mode pm8.1 (note) p8.1 i/o mode selection flag 0 set p8.1 to input mode 1 set p8.1 to output mode pm8.0 (note) p8.0 i/o mode selection flag 0 set p8.0 to input mode 1 set p8.0 to output mode note: p8 is dedicated for caller id interfacing. (refer to chapter 7)
memory map s3p7588x 4- 26 pne 1 ? port open-drain enable register fdbh, fdah bit 7 6 5 4 3 2 1 0 identifier pne5.3 pne5.2 pne5.1 pne5.0 pne4.3 pne4.2 pne4.1 pne4.0 reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 pne5.3 p5.3 output mode control bit 0 push-pull output 1 n-channel open-drain output pne5.2 p5.2 output mode control bit 0 push-pull output 1 n-channel open-drain output pne5.1 p5.1 output mode control bit 0 push-pull output 1 n-channel open-drain output pne5.0 p5.0 output mode control bit 0 push-pull output 1 n-channel open-drain output pne4.3 p4.3 output mode control bit 0 push-pull output 1 n-channel open-drain output pne4.2 p4.2 output mode control bit 0 push-pull output 1 n-channel open-drain output pne4.1 p4.1 output mode control bit 0 push-pull output 1 n-channel open-drain output pne4.0 p4.0 output mode control bit 0 push-pull output 1 n-channel open-drain output
s3p7588x memory map 4- 27 pumod1 ? pull-up resistor mode register 1 i/o fddh, fdc bit 7 6 5 4 3 2 1 0 identifier pur5 pur4 pur3 pur2 pur1.3 pur1.2 pur1.1 ?0? reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 pur5 connect/disconnect port 5 pull-up resistor control bit 0 disconnect port 5 pull-up resistor 1 connect port 5 pull-up resistor pur4 connect/disconnect port 4 pull-up resistor control bit 0 disconnect port 4 pull-up resistor 1 connect port 4 pull-up resistor pur3 connect/disconnect port 3 pull-up resistor control bit 0 disconnect port 3 pull-up resistor 1 connect port 3 pull-up resistor pur2 connect/disconnect port 2 pull-up resistor control bit 0 disconnect port 2 pull-up resistor 1 connect port 2 pull-up resistor pur1.3 connect/disconnect p1.3 pull-up resistor control bit 0 disconnect p1.3 pull-up resistor 1 connect p1.3 pull-up resistor pur1.2 connect/disconnect p1.2 pull-up resistor control bit 0 disconnect p1.2 pull-up resistor 1 connect p1.2 pull-up resistor pur1.1 connect/disconnect p1.1 pull-up resistor control bit 0 disconnect p1.1 pull-up resistor 1 connect p1.1 pull-up resistor .0 bit 0 0 always logic zero
memory map s3p7588x 4- 28 pumod2 ? pull-up resistor mode register 2 i/o fdeh bit 3 2 1 0 identifier pur9 pur8 note) pur7 pur6 reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 pur9 connect/disconnect port 9 pull-up resistor control bit 0 disconnect port 9 pull-up resistor 1 connect port 9 pull-up resistor pur8 (note) connect/disconnect port 8 pull-down resistor control bit 0 disconnect port 8 pull-down resistor 1 connect port 8 pull-down resistor pur7 connect/disconnect port 7 pull-up resistor control bit 0 disconnect port 7 pull-up resistor 1 connect port 7 pull-up resistor pur6 connect/disconnect port 6 pull-up resistor control bit 0 disconnect port 6 pull-up resistor 1 connect port 6 pull-up resistor note: p8 is dedicated for caller id interfacing. (r efer to chapter 7)
s3p7588x memory map 4- 29 tmod0 ? timer/counter 0 mode register t/c0 f91h, f90h bit 3 2 1 0 3 2 1 0 identifier ?0? .6 .5 .4 .3 .2 ?0? ?0? reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 1/8 8 8 8 tmod0.7 bit 7 0 always logic zero tmod0.6 ? .4 timer/counter 0 input clock selection bits 0 0 0 external clock input at tcl0 pin on rising edge 0 0 1 external clock input at tcl0 pin on falling edge 1 0 0 internal system clock fx/2 10 (4.09khz) 1 0 1 select clock: fx/2 6 (65.5khz) 1 1 0 select clock: fx/2 4 (262khz) 1 1 1 select clock: fx (4.19mhz) tmod0.3 clear counter and resume counting control bit 1 clears tcnt0 and irqt0. tol0 is remained and resume counting immediately (this bit is cleared automatically when counting starts.) tmod0.2 enable/disable timer/counter 0 bit 0 disable timer/counter 0; retain tcnt0 contents 1 enable timer/counter 0 tmod0.1 bit 1 0 always logic zero tmod0.0 bit 0 0 always logic zero
memory map s3p7588x 4- 30 tmod1 ? timer/counter 1 mode register t/c1 fa1h, fa0h bit 3 2 1 0 3 2 1 0 identifier ?0? .6 .5 .4 .3 .2 ?0? ?0? reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 1/8 8 8 8 tmod1.7 bit 7 0 always logic zero tmod1.6 ? .4 timer/counter 0 input clock selection bits 0 0 0 external clock input at tcl1 pin on rising edge 0 0 1 external clock input at tcl1 pin on falling edge 1 0 0 internal system clock fx/2 12 (1.02khz) 1 0 1 select clock: fx/2 10 (4.09khz) 1 1 0 select clock: fx/2 8 (16.4khz) 1 1 1 select clock: fx/2 6 (65.5khz) tmod1.3 clear counter and resume counting control bit 1 clears tcnt1 and irqt1. tol1 is remained and resume counting immediately (this bit is cleared automatically when counting starts.) tmod1.2 enable/disable timer/counter 0 bit 0 disable timer/counter 1; retain tcnt1 contents 1 enable timer/counter 1 tmod1.1 bit 1 0 always logic zero tmod1.0 bit 0 0 always logic zero
s3p7588x memory map 4- 31 toe ? timer output enable flag register t/c f92h bit 3 2 1 0 identifier toe1 toe0 boe ?0? reset reset value 0 0 0 0 read/write r/w r/w r/w w bit addressing 1/4 1/4 1/4 1/4 toe1 timer/counter 1 output enable flag 0 disable timer/counter 1 output to the tclo1 pin 1 enable timer/counter 1 output to the tclo1 pin toe0 timer/counter 0 output enable flag 0 disable timer/counter 0 output at the tclo0 pin 1 enable timer/counter 0 output at the tclo0 pin boe basic timer output enable flag 0 disable basic timer output at the btco pin 1 enable basic timer output at the btco pin .0 bit 0 0 always logic zero
memory map s3p7588x 4- 32 wdmod ? watchdog timer mode register f99h, f98h bit 7 6 5 4 3 2 1 0 identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 1 0 1 0 0 1 0 1 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 wdmod watchdog timer enable/disable control 5ah disable watchdog timer function any other value enable watchdog timer function
s3p7588x memory map 4- 33 wdflag ? watchdog timer counter clear flag register f9ah bit 3 2 1 0 identifier wdtcf ?0? ?0? ?0? reset reset value 0 0 0 0 read/write w w w w bit addressing 1/4 1/4 1/4 1/4 wdtcf watchdog timer counter clear flag 1 clears the watchdog timer counter .2?.0 bits 2-0 0 always logic zero note: after watchdog timer is cleared by writing ?1?, this bit is cleared to ?0? a utomatically.
memory map s3p7588x 4- 34 wmod ? watch timer mode register wt f89h, f88h bit 3 2 1 0 3 2 1 0 identifier .7 ?0? .5 .4 ?0? .2 .1 ?0? reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 wmod.7 enable/disable buzzer output bit 0 disable buzzer (buz) signal output 1 enable buzzer (buz) signal output wmod.6 bit 6 0 always logic zero wmod.5 ? .4 output buzzer frequency selection bits 0 0 fw/16 buzzer (buz) signal output (2khz) 0 1 fw/8 buzzer (buz) signal output (4khz) 1 0 fw/4 buzzer (buz) signal output (8khz) 1 1 fw/2 buzzer (buz) signal output (16khz) wmod.3 bit 3 0 always logic zero wmod.2 enable/disable watch timer bit 0 disable watch timer and clear frequency dividing circuits 1 enable watch timer wmod.1 watch timer speed control bit 0 normal speed; set irqw to 0.5 seconds 1 high-speed operation; set irqw to 3.91ms wmod.0 bit 0 0 always logic zero note: system clock of 4.19mhz is assumed.
s3p7588x instructio n set 5- 1 5 instruction set overview the instruction set includes 1-bit, 4-bit, and 8-bit instructions for data manipulation, logical and arithmetic operations, program control, and cpu control. i/o instructions for peripheral hardware devices are flexible and easy to use. symbolic hardware names can be substituted as the instruction operand in place of the actual address. other important features of the instruction set include: ? 1-byte referencing of long instructions (ref instruction) ? redundant instruction reduction (string effect) ? skip feature for adc and sbc instructions instruction operands conform to the operand format defined for each instruction. several instructions have multiple operand formats. predefined values or labels can be used as instruction operands when addressing immediate data. many of the symbols for specific registers and flags may also be substituted as labels for operations such da, mema, memb, b, and so on. using instruction labels can greatly simplify program writing and debugging tasks. instruction set features in this section, the following instruction set features are described in detail: ? instruction reference area ? instruction redundancy reduction ? flexible bit manipulation ? adc and sbc instruction skip condition
instruction set s3p 7588x 5- 2 instruction reference area using the 1-byte ref ( reference) instruction, you can reference instructions stored in addresses 0020h?007fh of program memory (the ref instruction look-up table). the location referenced by ref may contain either two 1-byte instructions or a single 2-byte instruction. the starting address of the instruction being referenced must always be an even number. 3-byte instructions such as jp or call may also be referenced using ref. to reference these 3-byte instructions, the 2-byte pseudo commands tjp and tcall must be written in the reference. the pc is not incremented when a ref instruction is executed. after it executes, the program's instruction execution sequence resumes at the address immediately following the ref instruction. by using ref instructions to execute instructions larger than one byte, as well as branches and subroutines, you can reduce the total number of program steps. to summarize, the ref instruction can be used in three ways: ? using the 1-byte ref instruction to execute one 2-byte or two 1-byte instructions; ? branching to any location by referencing a branch address that is stored in the look-up table; ? calling subroutines at any location by referencing a call address that is stored in the look-up table. if necessary, a ref instruction can be circumvented by means of a skip operation prior to the ref in the execution sequence. in addition, the instruction immediately following a ref can also be skipped by using an appropriate reference instruction or instructions. two-byte instructions which can be referenced using a ref instruction are limited to instructions with an execution time of two machine cycles. (an exception to this rule is xch a,da. ) in addition, when you use ref to reference two 1-byte instructions stored in the reference area, specific combinations must be used for the first and second 1-byte instruction. these combinations are described in table 5-1. table 5-1. valid 1-byte instruction combinations for ref look-ups first 1-byte instruction second 1-byte instruction instruction operand instruction operand ld a,@hl incs l ld @hl,a decs l decs h incs hl ld a,@wx incs x incs w decs w incs wx ld a,@wl incs l incs w decs w note: if the msb value of the first one-byte instruction is "0", the instruction cannot be referenced by a ref instruction.
s3p7588x instructio n set 5- 3 reducing instruction redundancy when redundant instructions such as ld a,#im and ld ea,#imm are used consecutively in a program sequence, only the first instruction is executed. the redundant instructions which follow are ignored, that is, they are handled like a nop instruction. when ld hl,#imm instructions are used consecutively, redundant instructions are also ignored. in the following example, only the 'ld a, # im' instruction will be executed. the 8-bit load instruction which follows it is interpreted as redundant and is ignored: ld a,#im ; load 4-bit immediate data (# im) to accumulator ld ea,#imm ; l oad 8-bit immediate data (# imm) to extended accumulator in this example, the statements 'ld a,#2h' and 'ld a,#3h' are ignored: bitr emb ld a,#1h ; execute instruction ld a,#2h ; ignore, redundant instruction ld a,#3h ; ignore, redundant instruction ld 23h,a ; execute instruction, 023h ? #1h if consecutive ld hl, # imm instructions (load 8-bit immediate data to the 8-bit memory pointer pair, hl) are detected, only the first ld is executed and the lds which immediately follow are ignored. for example, ld hl,#10h ; hl ? 10h ld hl,#20h ; ignore, redundant instruction ld a,#3h ; a ? 3h ld ea,#35h ; ignore, redundant instruction ld @hl,a ; (10h) ? 3h if an instruction reference with a ref instruction has a redundancy effect, the following conditions apply: ? if the instruction preceding the ref has a redundancy effect, this effect is cancelled and the referenced instruction is not skipped. ? if the instruction following the ref has a redundancy effect, the instruction following the ref is skipped.
instruction set s3p 7588x 5- 4 f f p rogramming tip ? example of the instruction redundancy effect org 0020h abc ld ea,#30h ; stored in ref instruction reference area org 0080h ? ? ? ld ea,#40h ; redundancy effect is encountered ref abc ; no skip (ea ? #30h) ? ? ? ref ab c ; ea ? #30h ld ea,#50h ; skip
s3p7588x instructio n set 5- 5 flexible bit manipulation in addition to normal bit manipulation instructions like set and clear, the instruction set can also perform bit tests, bit transfers, and bit boolean operations. bits can also be addressed and manipulated by special bit addressing modes. three types of bit addressing are supported: ? mema.b ? memb.@l ? @ h+da.b the parameters of these bit addressing modes are described in more detail in table 5-2. table 5-2. bit addressing modes and parameters addressing mode addressable peripherals address range mema.b erb, emb, is1, is0, iex, irqx fb0h?fbfh ports 1?9 ff1h?ff9h memb.@l ports 1?9, and bsc fc0h?ff9h @ h+da.b all bit- manipulable peripheral hardware all bits of the memory bank specified by emb and smb that are bit- manipulable instructions which have skip conditions the following instructions have a skip function when an overflow or borrow occurs: xchi incs xchd decs ldi ads ldd sbs if there is an overflow or borrow from the result of an increment or decrement, a skip signal is generated and a skip is executed. however, the carry flag value is unaffected. the instructions btst, btsf, and cpse also generate a skip signal and execute a skip when they meet a skip condition, and the carry flag value is also unaffected. instructions which affect the carry flag the only instructions which do not generate a skip signal, but which do affect the carry flag are as follows: adc ldb c,(operand) sbc band c,(operand) scf bor c,(operand) rcf bxor c,(operand) ccf iret rrc
instruction set s3p 7588x 5- 6 adc and sbc instruction skip conditions the instructions 'adc a,@hl' and 'sbc a,@hl' can generate a skip signal, and set or clear the carry flag, when they are executed in combination with the instruction 'ads a,#im'. if an 'ads a,#im' instruction immediately follows an 'adc a,@hl' or 'sbc a,@hl' instruction in a program sequence, the ads instruction does not skip the instruction following ads, even if it has a skip function. if, however, an 'adc a,@hl' or 'sbc a,@hl' instruction is immediately followed by an 'ads a,#im' instruction, the adc (or sbc) skips on overflow (or if there is no borrow) to the instruction immediately following the ads, and program execution continues. table 5-3 contains additional information and examples of the 'adc a,@hl' and 'sbc a,@hl' skip feature. table 5-3. skip conditions for adc and sbc instructions sample instruction sequences if the result of instruction 1 is: then, the execution sequence is: reason adc a,@hl ads a,#im xxx xxx 1 2 3 4 overflow no overflow 1, 3, 4 1, 2, 3, 4 ads cannot skip instruc- tion 3, even if it has a skip function. sbc a,@hl ads a,#im xxx xxx 1 2 3 4 borrow no borrow 1, 2, 3, 4 1, 3, 4 ads cannot skip instruc- tion 3, even if it has a skip function.
s3p7588x instructio n set 5- 7 symbols and conventions table 5-4. data type symbols symbol data type d immediate data a address data b bit data r register data f flag data i indirect addressing data t memc 0.5 immediate data table 5-5. register identifiers full register name id 4-bit accumulator a 4-bit working registers e, l, h, x, w, z, y 8-bit extended accumulator ea 8-bit memory pointer hl 8-bit working registers wx, yz, wl select register bank 'n' srb n select memory bank 'n' smb n carry flag c program status word psw port 'n' pn 'm'- th bit of port 'n' pn.m interrupt priority register ipr enable memory bank flag emb enable register bank flag erb table 5-6. instruction operand notation symbol definition da direct address @ indirect address prefix src source operand dst destination operand (r) contents of register r .b bit location im 4-bit immediate data (number) imm 8-bit immediate data (number) # immediate data prefix adr 000h?1fffh immediate address adrn 'n' bit address r a, e, l, h, x, w, z, y ra e, l, h, x, w, z, y rr ea, hl, wx, yz rra hl, wx, wl rrb hl, wx, yz rrc wx, wl mema fb0h?fbfh, ff1h?ff9h memb fc0h?ff9h memc code direct addressing: 0020h?007fh sb select bank register (8 bits) xor logical exclusive-or or logical or and logical and [(rr)] contents addressed by rr
instruction set s3p 7588x 5- 8 opcode definitions table 5-7. opcode definitions (direct) register r2 r1 r0 a 0 0 0 e 0 0 1 l 0 1 0 h 0 1 1 x 1 0 0 w 1 0 1 z 1 1 0 y 1 1 1 ea 0 0 0 hl 0 1 0 wx 1 0 0 yz 1 1 0 table 5-8. opcode definitions (indirect) register i2 i1 i0 @hl 1 0 1 @wx 1 1 0 @wl 1 1 1 i = immediate data for indirect addressing r = immediate data for register calculating additional machine cycles for skips a machine cycle is defined as one cycle of the selected cpu clock. three different clock rates can be selected using the pcon register. in this document, the letter 's' is used in tables when describing the number of additional machine cycles re quired for an instruction to execute, given that the instruction has a skip function ('s' = skip). the addition number of machine cycles that will be required to perform the skip usually depends on the size of the instruction being skipped ? whether it is a 1-byte, 2-byte, or 3-byte instruction. a skip is also executed for smb and srb instructions. the values in additional machine cycles for 's' for the three cases in which skip conditions occur are as follows: case 1: no skip s = 0 cycles case 2: skip is 1-byte or 2-byte instruction s = 1 cycle case 3: skip is 3-byte instruction s = 2 cycles note ref instructions are skipped in one machine cycle.
s3p7588x instructio n set 5- 9 high-level summary this section contains a high-level summary of the instruction set in table format. the tables are designed to familiarize you with the range of instructions that are available in each instruction category. these tables are a useful quick-reference resource when writing application programs. if you are reading this user's manual for the first time, however, you may want to scan this detailed information briefly, and then return to it later on. the following information is provided for each instruction: ? instruction name ? operand(s) ? brief operation description ? number of bytes of the instruction and operand(s) ? number of machine cycles required to execute the instruction the tables in this section are arranged according to the following instruction categories: ? cpu control instructions ? program control instructions ? data transfer instructions ? logic instructions ? arithmetic instructions ? bit manipulation instructions
instruction set s3p 7588x 5- 10 table 5-9. cpu control instructions ? high-level summary name operand operation description bytes cycles scf set carry flag to logic one 1 1 rcf reset carry flag to logic zero 1 1 ccf complement carry flag 1 1 ei enable all interrupts 2 2 di disable all interrupts 2 2 idle engage cpu idle mode 2 2 stop engage cpu stop mode 2 2 nop no operation 1 1 smb n select memory bank 2 2 srb n select register bank 2 2 ref memc reference code 1 3 ventn emb (0,1) erb (0,1) adr load enable memory bank flag (emb) and the enable register bank flag (erb) and program counter to vector address, then branch to the corresponding location 2 2 table 5-10. program control instructions ? high-level summary name operand operation description bytes cycles cpse r,#im compare and skip if register equals # im 2 2 + s @ hl,#im compare and skip if indirect data memory equals # im 2 2 + s a,r compare and skip if a equals r 2 2 + s a,@hl compare and skip if a equals indirect data memory 1 1 + s ea,@hl compare and skip if ea equals indirect data memory 2 2 + s ea,rr compare and skip if ea equals rr 2 2 + s jp adr14 jump to direct address (14 bits) 3 3 jps adr12 jump direct in page (12 bits) 2 2 jr # im jump to immediate address 1 2 @wx branch relative to wx register 2 3 @ea branch relative to ea 2 3 call adr14 call direct in page (14 bits) 3 4 calls adr11 call direct in page (11 bits) 2 3 ret ? return from subroutine 1 3 iret ? return from interrupt 1 3 sret ? return from subroutine and skip 1 3 + s
s3p7588x instructio n set 5- 11 table 5-11. data transfer instructions ? high-level summary name operand operation description bytes cycles xch a,da exchange a and direct data memory contents 2 2 a,ra exchange a and register ( ra) contents 1 1 a,@rra exchange a and indirect data memory 1 1 ea,da exchange ea and direct data memory con tents 2 2 ea,rrb exchange ea and register pair ( rrb) contents 2 2 ea,@hl exchange ea and indirect data memory con tents 2 2 xchi a,@hl exchange a and indirect data memory contents; increment contents of register l and skip on carry 1 2 + s xchd a,@hl exchange a and indirect data memory contents; decrement contents of register l and skip on carry 1 2 + s ld a,#im load 4-bit immediate data to a 1 1 a,@rra load indirect data memory contents to a 1 1 a,da load direct data memory contents to a 2 2 a,ra load register contents to a 2 2 ra,#im load 4-bit immediate data to register 2 2 rr,#imm load 8-bit immediate data to register 2 2 da,a load contents of a to direct data memory 2 2 ra,a load contents of a to register 2 2 ea,@hl load indirect data memory contents to ea 2 2 ea,da load direct data memory contents to ea 2 2 ea,rrb load register contents to ea 2 2 @hl,a load contents of a to indirect data memory 1 1 da,ea load contents of ea to data memory 2 2 rrb,ea load contents of ea to register 2 2 @hl,ea load contents of ea to indirect data memory 2 2 ldi a,@hl load indirect data memory to a; increment register l contents and skip on carry 1 2 + s ldd a,@hl load indirect data memory contents to a; decrement register l contents and skip on carry 1 2 + s ldc ea,@wx load code byte from wx to ea 1 3 ea,@ea load code byte from ea to ea 1 3 rrc a rotate right through carry bit 1 1 push rr push register pair onto stack 1 1 sb push smb and srb values onto stack 2 2 pop rr pop to register pair from stack 1 1 sb pop smb and srb values from stack 2 2
instruction set s3p 7588x 5- 12 table 5-12. logic instructions ? high-level summary name operand operation description bytes cycles and a,#im logical-and a immediate data to a 2 2 a,@hl logical-and a indirect data memory to a 1 1 ea,rr logical-and register pair (rr) to ea 2 2 rrb,ea logical-and ea to register pair ( rrb) 2 2 or a, # im logical-or immediate data to a 2 2 a, @hl logical-or indirect data memory contents to a 1 1 ea,rr logical-or double register to ea 2 2 rrb,ea logical-or ea to double register 2 2 xor a,#im exclusive-or immediate data to a 2 2 a,@hl exclusive-or indirect data memory to a 1 1 ea,rr exclusive-or register pair (rr) to ea 2 2 rrb,ea exclusive-or register pair ( rrb) to ea 2 2 com a complement accumulator (a) 2 2 table 5-13. arithmetic instructions ? high-level summary name operand operation description bytes cycles adc a,@hl add indirect data memory to a with carry t 1 ea,rr add register pair (rr) to ea with carry 2 2 rrb,ea add ea to register pair ( rrb) with carry 2 2 ads a, # im add 4-bit immediate data to a and skip on carry 1 1 + s ea,#imm add 8-bit immediate data to ea and skip on carry 2 2 + s a,@hl add indirect data memory to a and skip on carry 1 1 + s ea,rr add register pair (rr) contents to ea and skip on carry 2 2 + s rrb,ea add ea to register pair ( rrb) and skip on carry 2 2 + s sbc a,@hl subtract indirect data memory from a with carry 1 1 ea,rr subtract register pair (rr) from ea with carry 2 2 rrb,ea subtract ea from register pair ( rrb) with carry 2 2 sbs a,@hl subtract indirect data memory from a; skip on borrow 1 1 + s ea,rr subtract register pair (rr) from ea; skip on borrow 2 2 + s rrb,ea subtract ea from register pair ( rrb); skip on borrow 2 2 + s decs r decrement register (r); skip on borrow 1 1 + s rr decrement register pair (rr); skip on borrow 2 2 + s incs r increment register (r); skip on carry 1 1 + s da increment direct data memory; skip on carry 2 2 + s @hl increment indirect data memory; skip on carry 2 2 + s rrb increment register pair ( rrb); skip on carry 1 1 + s
s3p7588x instructio n set 5- 13 table 5-14. bit manipulation instructions ? high-level summary name operand operation description bytes cycles btst c test specified bit and skip if carry flag is set 1 1 + s da.b test specified bit and skip if memory bit is set 2 2 + s mema.b memb.@l @ h+da.b btsf da.b test specified memory bit and skip if bit equals "0" mema.b memb.@l @ h+da.b btstz mema.b test specified bit; skip and clear if memory bit is set memb.@l @ h+da.b bits da.b set specified memory bit 2 2 mema.b memb.@l @ h+da.b bitr da.b clear specified memory bit to logic zero mema.b memb.@l @ h+da.b band c,mema.b logical-and carry flag with specified memory bit c,memb.@l c,@h+da.b bor c,mema.b logical-or carry with specified memory bit c,memb.@l c,@h+da.b bxor c,mema.b exclusive-or carry with specified memory bit c,memb.@l c,@h+da.b ldb mema.b,c load carry bit to a specified memory bit memb.@l,c load carry bit to a specified indirect memory bit @ h+da.b,c c,mema.b load specified memory bit to carry bit c,memb.@l load specified indirect memory bit to carry bit c,@h+da.b
instruction set s3p 7588x 5- 14 binary code summary this section contains binary code values and operation notation for each instruction in the instruction set in an easy-to-read, tabular format. it is intended to be used as a quick-reference source for programmers who are experienced with the instruction set. the same binary values and notation are also included in the detailed descriptions of individual instructions later in section 5. if you are reading this user's manual for the first time, please just scan this very detailed information briefly. most of the general information you will need to write application programs can be found in the high-level sum mary tables in the previous section. the following information is provided for each instruction: ? instruction name ? operand(s) ? binary values ? operation notation the tables in this section are arranged according to the following instruction categories: ? cpu control instructions ? program control instructions ? data transfer instructions ? logic instructions ? arithmetic instructions ? bit manipulation instructions
s3p7588x instructio n set 5- 15 table 5-15. cpu control instructions ? binary code summary name operand binary code operation notation scf 1 1 1 0 0 1 1 1 c ? 1 rcf 1 1 1 0 0 1 1 0 c ? 0 ccf 1 1 0 1 0 1 1 0 c ? c ei 1 1 1 1 1 1 1 1 ime ? 1 1 0 1 1 0 0 1 0 di 1 1 1 1 1 1 1 0 ime ? 0 1 0 1 1 0 0 1 0 idle 1 1 1 1 1 1 1 1 pcon.2 ? 1 1 0 1 0 0 0 1 1 stop 1 1 1 1 1 1 1 1 pcon.3 ? 1 1 0 1 1 0 0 1 1 nop 1 0 1 0 0 0 0 0 no operation smb n 1 1 0 1 1 1 0 1 smb ? n (n = 0, 1, 15) 0 1 0 0 d3 d2 d1 d0 srb n 1 1 0 1 1 1 0 1 srb ? n (n = 0, 1, 2, 3) 0 1 0 1 0 0 d1 d0 ref memc t7 t6 t5 t4 t3 t2 t1 t0 pc12?0 = memc7?4, memc3?0 <1 ventn emb (0,1) erb (0,1) adr e m b e r b 0 a12 a11 a10 a9 a8 rom (2 x n) 7?6 ? emb, erb rom (2 x n) 5?4 ? 0, pc12 rom (2 x n) 3?0 ? pc12?8 rom (2 x n + 1) 7?0 ? pc7?0 (n = 0, 1, 2, 3, 4, 5, 6, 7) a7 a6 a5 a4 a3 a2 a1 a0
instruction set s3p 7588x 5- 16 table 5-16. program control instructions ? binary code summary name operand binary code operation notation cpse r,#im 1 1 0 1 1 0 0 1 skip if r = im d3 d2 d1 d0 0 r2 r1 r0 @ hl,#im 1 1 0 1 1 1 0 1 skip if (hl) = im 0 1 1 1 d3 d2 d1 d0 a,r 1 1 0 1 1 1 0 1 skip if a = r 0 1 1 0 1 r2 r1 r0 a,@hl 0 0 1 1 1 0 0 0 skip if a = (hl) ea,@hl 1 1 0 1 1 1 0 0 skip if a = (hl), e = (hl+1) 0 0 0 0 1 0 0 1 ea,rr 1 1 0 1 1 1 0 0 skip if ea = rr 1 1 1 0 1 r2 r1 0 jp adr14 1 1 0 1 1 0 1 1 pc12?0 ? adr14 0 0 0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 jps adr12 1 0 0 1 a11 a10 a9 a8 pc12?0 ? pc12 + adr11?0 a7 a6 a5 a4 a3 a2 a1 a0 jr # im * pc12?0 ? adr (pc?15 to pc+16) @wx 1 1 0 1 1 1 0 1 pc12?0 ? pc12?8 + (wx) 0 1 1 0 0 1 0 0 @ea 1 1 0 1 1 1 0 1 pc12?0 ? pc12?8 + (ea) 0 1 1 0 0 0 0 0 call adr14 1 1 0 1 1 0 1 1 [(sp?1) (sp?2)] ? emb, erb 0 1 0 a12 a11 a10 a9 a8 [(sp?3) (sp?4)] ? pc7?0 a7 a6 a5 a4 a3 a2 a1 a0 [(sp?5) (sp?6)] ? pc12?8 calls adr11 1 1 1 0 1 a10 a9 a8 [(sp?1) (sp?2)] ? emb, erb a7 a6 a5 a4 a3 a2 a1 a0 [(sp?3) (sp?4)] ? pc7?0 [(sp?5) (sp?6)] ? pc10?8 first byte condition * jr # im 0 0 0 1 a3 a2 a1 a0 pc ? pc+2 to pc+16 0 0 0 0 a3 a2 a1 a0 pc ? pc?1 to pc?15
s3p7588x instructio n set 5- 17 table 5-16. program control instructions ? binary code summary (continued) name operand binary code operation notation ret ? 1 1 0 0 0 1 0 1 pc12?8 ? (sp + 1) (sp) pc7?0 ? (sp + 2) (sp + 3) emb,erb ? (sp + 5) (sp + 4) sp ? sp + 6 iret ? 1 1 0 1 0 1 0 1 pc12?8 ? (sp + 1) (sp) pc7?0 ? (sp + 2) (sp + 3) psw ? (sp + 4) (sp + 5) sp ? sp + 6 sret ? 1 1 1 0 0 1 0 1 pc12?8 ? (sp + 1) (sp) pc7?0 ? (sp + 3) (sp + 2) emb,erb ? (sp + 5) (sp + 4) sp ? sp + 6 table 5-17. data transfer instructions ? binary code summary name operand binary code operation notation xch a,da 0 1 1 1 1 0 0 1 a ? da a7 a6 a5 a4 a3 a2 a1 a0 a,ra 0 1 1 0 1 r2 r1 r0 a ? ra a,@rra 0 1 1 1 1 i2 i1 i0 a ? ( rra) ea,da 1 1 0 0 1 1 1 1 a ? da,e ? da + 1 a7 a6 a5 a4 a3 a2 a1 a0 ea,rrb 1 1 0 1 1 1 0 0 ea ? rrb 1 1 1 0 0 r2 r1 0 ea,@hl 1 1 0 1 1 1 0 0 a ? (hl), e ? (hl + 1) 0 0 0 0 0 0 0 1 xchi a,@hl 0 1 1 1 1 0 1 0 a ? (hl), then l ? l+1; skip if l = 0h xchd a,@hl 0 1 1 1 1 0 1 1 a ? (hl), then l ? l-1; skip if l = 0fh ld a,#im 1 0 1 1 d3 d2 d1 d0 a ? im a,@rra 1 0 0 0 1 i2 i1 i0 a ? ( rra) a,da 1 0 0 0 1 1 0 0 a ? da a7 a6 a5 a4 a3 a2 a1 a0 a,ra 1 1 0 1 1 1 0 1 a ? ra 0 0 0 0 1 r2 r1 r0
instruction set s3p 7588x 5- 18 table 5-17. data transfer instructions ? binary code summary (continued) name operand binary code operation notation ld ra,#im 1 1 0 1 1 0 0 1 ra ? im d3 d2 d1 d0 1 r2 r1 r0 rr,#imm 1 0 0 0 0 r2 r1 1 rr ? imm d7 d6 d5 d4 d3 d2 d1 d0 da,a 1 0 0 0 1 0 0 1 da ? a a7 a6 a5 a4 a3 a2 a1 a0 ra,a 1 1 0 1 1 1 0 1 ra ? a 0 0 0 0 0 r2 r1 r0 ea,@hl 1 1 0 1 1 1 0 0 a ? (hl), e ? (hl + 1) 0 0 0 0 1 0 0 0 ea,da 1 1 0 0 1 1 1 0 a ? da, e ? da + 1 a7 a6 a5 a4 a3 a2 a1 a0 ea,rrb 1 1 0 1 1 1 0 0 ea ? rrb 1 1 1 1 1 r2 r1 0 @hl,a 1 1 0 0 0 1 0 0 (hl) ? a da,ea 1 1 0 0 1 1 0 1 da ? a, da + 1 ? e a7 a6 a5 a4 a3 a2 a1 a0 rrb,ea 1 1 0 1 1 1 0 0 rrb ? ea 1 1 1 1 0 r2 r1 0 @hl,ea 1 1 0 1 1 1 0 0 (hl) ? a, (hl + 1) ? e 0 0 0 0 0 0 0 0 ldi a,@hl 1 0 0 0 1 0 1 0 a ? (hl), then l ? l+1; skip if l = 0h ldd a,@hl 1 0 0 0 1 0 1 1 a ? (hl), then l ? l?1; skip if l = 0fh ldc ea,@wx 1 1 0 0 1 1 0 0 ea ? [pc12?8 + (wx)] ea,@ea 1 1 0 0 1 0 0 0 ea ? [pc12?8 + (ea)] rrc a 1 0 0 0 1 0 0 0 c ? a.0, a3 ? c a.n?1 ? a.n (n = 1, 2, 3) push rr 0 0 1 0 1 r2 r1 1 ((sp?1)) ((sp?2)) ? (rr), (sp) ? (sp)?2 sb 1 1 0 1 1 1 0 1 ((sp?1)) ? (smb), ((sp?2)) ? (srb), (sp) ? (sp)?2 0 1 1 0 0 1 1 1
s3p7588x instructio n set 5- 19 table 5-17. data transfer instructions ? binary code summary (concluded) name operand binary code operation notation pop rr 0 0 1 0 1 r2 r1 0 rr l ? (sp), rr h ? (sp + 1) sp ? sp + 2 sb 1 1 0 1 1 1 0 1 (srb) ? (sp), smb ? (sp + 1), sp ? sp + 2 0 1 1 0 0 1 1 0 table 5-18. logic instructions ? binary code summary name operand binary code operation notation and a,#im 1 1 0 1 1 1 0 1 a ? a and im 0 0 0 1 d3 d2 d1 d0 a,@hl 0 0 1 1 1 0 0 1 a ? a and (hl) ea,rr 1 1 0 1 1 1 0 0 ea ? ea and rr 0 0 0 1 1 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 rrb ? rrb and ea 0 0 0 1 0 r2 r1 0 or a, # im 1 1 0 1 1 1 0 1 a ? a or im 0 0 1 0 d3 d2 d1 d0 a, @hl 0 0 1 1 1 0 1 0 a ? a or (hl) ea,rr 1 1 0 1 1 1 0 0 ea ? ea or rr 0 0 1 0 1 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 rrb ? rrb or ea 0 0 1 0 0 r2 r1 0 xor a,#im 1 1 0 1 1 1 0 1 a ? a xor im 0 0 1 1 d3 d2 d1 d0 a,@hl 0 0 1 1 1 0 1 1 a ? a xor (hl) ea,rr 1 1 0 1 1 1 0 0 ea ? ea xor (rr) 0 0 1 1 0 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 rrb ? rrb xor ea 0 0 1 1 0 r2 r1 0 com a 1 1 0 1 1 1 0 1 a ? a 0 0 1 1 1 1 1 1
instruction set s3p 7588x 5- 20 table 5-19. arithmetic instructions ? binary code summary name operand binary code operation notation adc a,@hl 0 0 1 1 1 1 1 0 c, a ? a + (hl) + c ea,rr 1 1 0 1 1 1 0 0 c, ea ? ea + rr + c 1 0 1 0 1 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 c, rrb ? rrb + ea + c 1 0 1 0 0 r2 r1 0 ads a, # im 1 0 1 0 d3 d2 d1 d0 a ? a + im; skip on carry ea,#imm 1 1 0 0 1 0 0 1 ea ? ea + imm; skip on carry d7 d6 d5 d4 d3 d2 d1 d0 a,@hl 0 0 1 1 1 1 1 1 a ? a+ (hl); skip on carry ea,rr 1 1 0 1 1 1 0 0 ea ? ea + rr; skip on carry 1 0 0 1 1 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 rrb ? rrb + ea; skip on carry 1 0 0 1 0 r2 r1 0 sbc a,@hl 0 0 1 1 1 1 0 0 c,a ? a ? (hl) ? c ea,rr 1 1 0 1 1 1 0 0 c, ea ? ea ?rr ? c 1 1 0 0 1 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 c,rrb ? rrb ? ea ? c 1 1 0 0 0 r2 r1 0 sbs a,@hl 0 0 1 1 1 1 0 1 a ? a ? (hl); skip on borrow ea,rr 1 1 0 1 1 1 0 0 ea ? ea ? rr; skip on borrow 1 0 1 1 1 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 rrb ? rrb ? ea; skip on borrow 1 0 1 1 0 r2 r1 0 decs r 0 1 0 0 1 r2 r1 r0 r ? r?1; skip on borrow rr 1 1 0 1 1 1 0 0 rr ? rr?1; skip on borrow 1 1 0 1 1 r2 r1 0 incs r 0 1 0 1 1 r2 r1 r0 r ? r + 1; skip on carry da 1 1 0 0 1 0 1 0 da ? da + 1; skip on carry a7 a6 a5 a4 a3 a2 a1 a0 @hl 1 1 0 1 1 1 0 1 (hl) ? (hl) + 1; skip on carry 0 1 1 0 0 0 1 0 rrb 1 0 0 0 0 r2 r1 0 rrb ? rrb + 1; skip on carry
s3p7588x instructio n set 5- 21 table 5-20. bit manipulation instructions ? binary code summary name operand binary code operation notation btst c 1 1 0 1 0 1 1 1 skip if c = 1 da.b 1 1 b1 b0 0 0 1 1 skip if da.b = 1 a7 a6 a5 a4 a3 a2 a1 a0 mema.b * 1 1 1 1 1 0 0 1 skip if mema.b = 1 memb.@l 1 1 1 1 1 0 0 1 skip if [memb.7?2 + l.3?2]. [l.1?0] = 1 0 1 0 0 a5 a4 a3 a2 @ h+da.b 1 1 1 1 1 0 0 1 skip if [h + da.3?0].b = 1 0 0 b1 b0 a3 a2 a1 a0 btsf da.b 1 1 b1 b0 0 0 1 0 skip if da.b = 0 a7 a6 a5 a4 a3 a2 a1 a0 mema.b * 1 1 1 1 1 0 0 0 skip if mema.b = 0 memb.@l 1 1 1 1 1 0 0 0 skip if [memb.7?2 + l.3?2]. [l.1?0] = 0 0 1 0 0 a5 a4 a3 a2 @h da.b 1 1 1 1 1 0 0 0 skip if [h + da.3?0].b = 0 0 0 b1 b0 a3 a2 a1 a0 btstz mema.b * 1 1 1 1 1 1 0 1 skip if mema.b = 1 and clear memb.@l 1 1 1 1 1 1 0 1 skip if [memb.7?2 + l.3?2]. [l.1?0] = 1 and clear 0 1 0 0 a5 a4 a3 a2 @ h+da.b 1 1 1 1 1 1 0 1 skip if [h + da.3?0].b =1 and clear 0 0 b1 b0 a3 a2 a1 a0 bits da.b 1 1 b1 b0 0 0 0 1 da.b ? 1 a7 a6 a5 a4 a3 a2 a1 a0 mema.b * 1 1 1 1 1 1 1 1 mema.b ? 1 memb.@l 1 1 1 1 1 1 1 1 [memb.7?2 + l.3?2].b [l.1?0] ? 1 0 1 0 0 a5 a4 a3 a2 @ h+da.b 1 1 1 1 1 1 1 1 [h + da.3?0].b ? 1 0 0 b1 b0 a3 a2 a1 a0
instruction set s3p 7588x 5- 22 table 5-20. bit manipulation instructions ? binary code summary (continued) name operand binary code operation notation bitr da.b 1 1 b1 b0 0 0 0 0 da.b ? 0 a7 a6 a5 a4 a3 a2 a1 a0 mema.b * 1 1 1 1 1 1 1 0 mema.b ? 0 memb.@l 1 1 1 1 1 1 1 0 [memb.7?2 + l3?2].[l.1?0] ? 0 0 1 0 0 a5 a4 a3 a2 @ h+da.b 1 1 1 1 1 1 1 0 [h + da.3?0].b ? 0 0 0 b1 b0 a3 a2 a1 a0 band c,mema.b * 1 1 1 1 0 1 0 1 c ? c and mema.b c,memb.@l 1 1 1 1 0 1 0 1 c ? c and [memb.7?2 + l.3?2]. [l.1?0] 0 1 0 0 a5 a4 a3 a2 c,@h+da.b 1 1 1 1 0 1 0 1 c ? c and [h + da.3?0].b 0 0 b1 b0 a3 a2 a1 a0 bor c,mema.b * 1 1 1 1 0 1 1 0 c ? c or mema.b c,memb.@l 1 1 1 1 0 1 1 0 c ? c or [memb.7?2 + l.3?2]. [l.1?0] 0 1 0 0 a5 a4 a3 a2 c,@h+da.b 1 1 1 1 0 1 1 0 c ? c or [h + da.3?0].b 0 0 b1 b0 a3 a2 a1 a0 bxor c,mema.b * 1 1 1 1 0 1 1 1 c ? c xor mema.b c,memb.@l 1 1 1 1 0 1 1 1 c ? c xor [memb.7?2 + l.3?2]. [l.1?0] 0 1 0 0 a5 a4 a3 a2 c,@h+da.b 1 1 1 1 0 1 1 1 c ? c xor [h + da.3?0].b 0 0 b1 b0 a3 a2 a1 a0 second byte bit addresses * mema.b 1 0 b1 b0 a3 a2 a1 a0 fb0h?fbfh 1 1 b1 b0 a3 a2 a1 a0 ff1h?ff9h
s3p7588x instructio n set 5- 23 table 5-20. bit manipulation instructions ? binary code summary (concluded) name operand binary code operation notation ldb mema.b,c * 1 1 1 1 1 1 0 0 mema.b ? c memb.@l,c 1 1 1 1 1 1 0 0 memb.7?2 + [l.3?2]. [l.1?0] ? c 0 1 0 0 a5 a4 a3 a2 @ h+da.b,c 1 1 1 1 1 1 0 0 h + [da.3?0].b ? (c) 0 b2 b1 b0 a3 a2 a1 a0 c,mema.b * 1 1 1 1 0 1 0 0 c ? mema.b c,memb.@l 1 1 1 1 0 1 0 0 c ? memb.7?2 + [l.3?2] . [l.1?0] 0 1 0 0 a5 a4 a3 a2 c,@h+da.b 1 1 1 1 0 1 0 0 c ? [h + da.3?0].b 0 b2 b1 b0 a3 a2 a1 a0 second byte bit addresses * mema.b 1 0 b1 b0 a3 a2 a1 a0 fb0h?fbfh 1 1 b1 b0 a3 a2 a1 a0 ff1h?ff9h
instruction set s3p 7588x 5- 24 instruction descriptions this section contains detailed information and programming examples for each instruction of the instruction set. information is arranged in a consistent format to improve readability and for use as a quick-reference re source for application programmers. if you are reading this user's manual for the first time, please just scan this very detailed information briefly in order to acquaint yourself with the basic features of the instruction set. the information elements of the instruction description format are as follows: ? instruction name (mnemonic) ? full instruction name ? source/destination format of the instruction operand ? operation overview (from the "high-level summary" table) ? textual description of the instruction's effect ? binary code overview (from the "bin ary code summary" table) ? programming example(s) to show how the instruction is used
s3p7588x instructio n set 5- 25 adc ? a dd with carry adc dst,src operation : operand operation summary bytes cycles a,@hl add indirect data memory to a with carry 1 1 ea,rr add register pair (rr) to ea with carry 2 2 rrb,ea add ea to register pair ( rrb) with carry 2 2 description: the source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination. the c ontents of the source are unaffected. if there is an overflow from the most significant bit of the ls is no overflow, the ads instruction is executed normally. (this condition is valid only for 'adc a,@hl' instructions. if an overflow occurs following an 'ads a,#im' instruction, the next instruction will not be skipped.) operand binary code operation notation a,@hl 0 0 1 1 1 1 1 0 c, a ? a + (hl) + c ea,rr 1 1 0 1 1 1 0 0 c, ea ? ea + rr + c 1 0 1 0 1 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 c, rrb ? rrb + ea + c 1 0 1 0 0 r2 r1 0 examples: 1. the extended accumulator contains the value 0c3h, register pair hl the value 0aah, and the carry flag is set to "1": scf ; c ? "1" adc ea,hl ; ea ? 0c3h + 0aah + 1h = 6eh, c ? "1" jps xxx ; jump to xxx; no skip after adc 2. if the extended accumulator con tains the value 0c3h, register pair hl the value 0aah, and the carry flag is cleared to "0": rcf ; c ? "0" adc ea,hl ; ea ? 0c3h + 0aah + 0h = 6eh, c ? "1" jps xxx ; jump to xxx; no skip after adc
instruction set s3p 7588x 5- 26 adc ? add with carry adc (continued) examples: 3. if adc a,@hl is followed by an ads a,#im, the adc skips on carry to the instruction immediately after the ads. an ads instruction immediately after the adc does not skip even if an overflow occurs. this function is useful for decimal adjustment operations. a. 8 + 9 decimal addition (the contents of the address specified by the hl register is 9h): rcf ; c ? "0" ld a,#8h ; a ? 8h ads a,#6h ; a ? 8h + 6h = 0eh adc a,@hl ; a ? 7h, c ? "1" ads a,#0ah ; skip this inst ruction because c = "1" after adc result jps xxx b. 3 + 4 decimal addition (the contents of the address specified by the hl register is 4h): rcf ; c ? "0" ld a,#3h ; a ? 3h ads a,#6h ; a ? 3h + 6h = 9h adc a,@hl ; a ? 9h + 4h + c(0) = 0dh ads a,#0ah ; no skip. a ? 0dh + 0ah = 7h ; (the skip function for 'ads a,#im' is inhibited after an ; 'adc a,@hl' instruction even if an overflow occurs.) jps xxx
s3p7588x instructio n set 5- 27 ads ? add and skip on overflow ads dst,src operation: operand operation summary bytes cycles a, # im add 4-bit immediate data to a and skip on overflow 1 1 + s ea,#imm add 8-bit immediate data to ea and skip on overflow 2 2 + s a,@hl add indirect data memory to a and skip on overflow 1 1 + s ea,rr add register pair (rr) contents to ea and skip on overflow 2 2 + s rrb,ea add ea to register pair ( rrb) and skip on overflow 2 2 + s description: the source operand is added to the destination operand and the sum is stored in the destination. the contents of the source are unaffected. if there is an overflow from the most significant bit of the result, the skip signal is generated and a skip is executed, but the carry flag value is unaffected. if 'ads a,#im' follows an 'adc a,@hl' instruction in a program, adc skips the ads instruction if an overflow occurs. if there is no overflow, the ads instruction is executed normally. this skip condition is valid only for 'adc a,@hl' instructions, however. if an overflow occurs following an ads instruction, the next instruction is not skipped. operand binary code operation notation a, # im 1 0 1 0 d3 d2 d1 d0 a ? a + im; skip on overflow ea,#imm 1 1 0 0 1 0 0 1 ea ? ea + imm; skip on overflow d7 d6 d5 d4 d3 d2 d1 d0 a,@hl 0 0 1 1 1 1 1 1 a ? a + (hl); skip on overflow ea,rr 1 1 0 1 1 1 0 0 ea ? ea + rr; skip on overflow 1 0 0 1 1 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 rrb ? rrb + ea; skip on overflow 1 0 0 1 0 r2 r1 0 examples: 1. the extended accumulator contains the value 0c3h, register pair hl the value 0aah, and the carry flag = "0": ads ea,hl ; ea ? 0c3h + 0aah = 6dh, c ? "0" ; ads skips on over flow, but carry flag value is not affected. jps xxx ; this instruction is skipped since ads had an overflow. jps yyy ; jump to yyy.
instruction set s3p 7588x 5- 28 ads ? add and skip on overflow ads (continued) examples: 2. if the extended accumulator contains the value 0c3h, register pair hl the value 12h, and the carry flag = "0": ads ea,hl ; ea ? 0c3h + 12h = 0d5h, c ? "0" jps xxx ; jump to xxx; no skip after ads. 3. if 'adc a,@hl' is followed by an 'ads a,#im', the adc skips on overflow to the instruction immediately after the ads. an 'ads a,#im' instruction immediately after the 'adc a,@hl' does not skip even if overflow occurs. this function is useful for decimal adjustment operations. a. 8 + 9 decimal addition (the contents of the address specified by the hl register is 9h): rcf ; c ? "0" ld a,#8h ; a ? 8h ads a,#6h ; a ? 8h + 6h = 0eh adc a,@hl ; a ? 7h, c ? "1" ads a,#0ah ; skip this instruction because c = "1" after adc result. jps xxx b. 3 + 4 decimal addition (the contents of the address specified by the hl register is 4h): rcf ; c ? "0" ld a,#3h ; a ? 3h ads a,#6h ; a ? 3h + 6h = 9h adc a,@hl ; a ? 9h + 4h + c(0) = 0dh ads a,#0ah ; no skip. a ? 0dh + 0ah = 7h ; (the skip function for 'ads a,#im' is inhibited after an ; 'adc a,@hl' instruction even if an overflow occurs.) jps xxx
s3p7588x instructio n set 5- 29 and ? logical and and dst,src operation: operand operation summary bytes cycles a,#im logical-and a immediate data to a 2 2 a,@hl logical-and a indirect data memory to a 1 1 ea,rr logical-and register pair (rr) to ea 2 2 rrb,ea logical-and ea to register pair ( rrb) 2 2 description: the source operand is logically anded with the destination operand. the result is stored in the destination. the logical and operation results in a "1" bit being stored whenever the corresponding bits in the two operands are both "1"; otherwise a "0" bit is stored. the contents of the source are unaffected. operand binary code operation notation a,#im 1 1 0 1 1 1 0 1 a ? a and im 0 0 0 1 d3 d2 d1 d0 a,@hl 0 0 1 1 1 0 0 1 a ? a and (hl) ea,rr 1 1 0 1 1 1 0 0 ea ? ea and rr 0 0 0 1 1 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 rrb ? rrb and ea 0 0 0 1 0 r2 r1 0 example: if the extended accumulator contains the value 0c3h (11000011b) and register pair hl the value 55h (01010101b), the instruction and ea,hl leaves the value 41h (01000001b) in the extended accumulator ea .
instruction set s3p 7588x 5- 30 band ? bit logical and band c,src.b operation: operand operation summary bytes cycles c,mema.b logical-and carry flag with memory bit 2 2 c,memb.@l 2 2 c,@h+da.b 2 2 description: the specified bit of the source is logically anded with the carry flag bit value. if the boolean value of the source bit is a logic zero, the carry flag is cleared to "0"; otherwise, the current carry flag setting is left unaltered. the bit value of the source operand is not affected. operand binary code operation notation c,mema.b * 1 1 1 1 0 1 0 1 c ? c and mema.b c,memb.@l 1 1 1 1 0 1 0 1 c ? c and [memb.7?2 + l.3? 2]. [l.1?0] 0 1 0 0 a5 a4 a3 a2 c,@h+da.b 1 1 1 1 0 1 0 1 c ? c and [h + da.3?0].b 0 0 b1 b0 a3 a2 a1 a0 second byte bit addresses * mema.b 1 0 b1 b0 a3 a2 a1 a0 fb0h?fbfh 1 1 b1 b0 a3 a2 a1 a0 ff1h?ff9h examples: 1. the following instructions set the carry flag if p1.0 (port 1.0) is equal to "1" (and assuming the carry flag is already set to "1"): smb 15 ; c ? "1" band c,p1.0 ; if p1.0 = "1", c ? "1" ; if p1.0 = "0", c ? "0" 2. assume the p1 address is ff1h and the value for register l is 9h (1001b). the address (memb.7?2) is 111100b; (l.3?2) is 10b. the resulting address is 11110010b or ff2h, specifying p2. the bit value for the band instruction, (l.1?0) is 01b which specifies bit 1. the refore, p1.@l = p2.1: ld l,#9h band c,p1.@l ; p1.@l is specified as p2.1 ; c and p2.1
s3p7588x instructio n set 5- 31 band ? bit logical and band (continued) examples: 3. register h contains the value 2h and flag = 20h.3. the address of h is 0010b and flag(3?0) is 0000b. the resulting address is 00100000b or 20h. the bit value for the band instruction is 3. therefore, @h+flag = 20h.3: flag equ 20h.3 ld h,#2h band c,@h+flag ; c and flag (20h.3)
instruction set s3p 7588x 5- 32 bitr ? bit reset bitr dst.b operation: operand operation summary bytes cycles da.b clear specified memory bit to logic zero 2 2 mema.b 2 2 memb.@l 2 2 @ h+da.b 2 2 description: a bitr instruction clears to logic zero (resets) the specified bit within the destination operand. no other bits in the destination are affected. operand binary code operation notation da.b 1 1 b1 b0 0 0 0 0 da.b ? 0 a7 a6 a5 a4 a3 a2 a1 a0 mema.b * 1 1 1 1 1 1 1 0 mema.b ? 0 memb.@l 1 1 1 1 1 1 1 0 [memb.7?2 + l3?2].[l.1?0] ? 0 0 1 0 0 a5 a4 a3 a2 @ h+da.b 1 1 1 1 1 1 1 0 [h + da.3?0].b ? 0 0 0 b1 b0 a3 a2 a1 a0 second byte bit addresses * mema.b 1 0 b1 b0 a3 a2 a1 a0 fb0h?fbfh 1 1 b1 b0 a3 a2 a1 a0 ff1h?ff9h examples: 1. bit location 30h.2 in the ram has a current value of logic one. the following instruction clears the third bit in ram location 30h (bit 2) to logic zero: bitr 30h.2 ; 30h. 2 ? "0" 2. you can use bitr in the same way to manipulate a port address bit: bitr p2.0 ; p2.0 ? "0"
s3p7588x instructio n set 5- 33 bitr ? bit reset bitr (continued) examples: 3. assuming that p2.2, p2.3, and p3.0?p3.3 are cleared to "0": ld l,#0ah bp2 bitr p1.@l ; first, p1.@0ah = p2.2 ; (111100b) + 10b.10b = 0f2h.2 incs l jr bp2 4. if bank 0, location 0a0h.0 is cleared (and regardless of whether the emb value is logic zero), bitr has the f ollowing effect: flag equ 0a0h.0 ? ? ? bitr emb ? ? ? ld h,#0ah bitr @h+flag ; bank 0 (ah + 0h).0 = 0a0h.0 ? "0? note: since the bitr instruction is used for output functions, the pin names used in the examples above may change for different devices in the product family.
instruction set s3p 7588x 5- 34 bits ? bit set bits dst.b operation: operand operation summary bytes cycles da.b set specified memory bit 2 2 mema.b 2 2 memb.@l 2 2 @ h+da.b 2 2 description: this instruction sets the specified bit within the destination without affecting any other bits in the destination. bits can manipulate any bit that is addressable using direct or indirect addressing modes. operand binary code operation notation da.b 1 1 b1 b0 0 0 0 1 da.b ? 1 a7 a6 a5 a4 a3 a2 a1 a0 mema.b * 1 1 1 1 1 1 1 1 mema.b ? 1 memb.@l 1 1 1 1 1 1 1 1 [memb.7?2 + l.3?2].b [l.1?0] ? 1 0 1 0 0 a5 a4 a3 a2 @ h+da.b 1 1 1 1 1 1 1 1 [h + da.3?0].b ? 1 0 0 b1 b0 a3 a2 a1 a0 second byte bit addresses * mema.b 1 0 b1 b0 a3 a2 a1 a0 fb0h?fbfh 1 1 b1 b0 a3 a2 a1 a0 ff1h?ff9h examples: 1. assuming that bit location 30h.2 in the ram has a current value of "0", the following instruction sets the second bit of location 30h to "1". bits 30h.2 ; 30h.2 ? "1" 2. you can use bits in the sa me way to manipulate a port address bit: bits p2.0 ; p2.0 ? "1"
s3p7588x instructio n set 5- 35 bits ? bit set bits (continued) examples: 3. given that p2.2, p2.3, and p3.0?p3.3 are set to "1": ld l,#0ah bp2 bits p1.@l ; first, p1.@0ah = p2.2 ; (111100b) + 10b.10b = 0f2h.2 incs l jr bp2 4. if bank 0, location 0a0h.0, is set to "1" and the emb = "0", bits has the following effect: flag equ 0a0h.0 ? ? ? bitr emb ? ? ? ld h,#0ah bits @h+flag ; bank 0 (ah + 0h).0 = 0a0h.0 ? "1" note: since the bits instruction is used for output functions, pin names used in the examples above may change for different devices in the product family.
instruction set s3p 7588x 5- 36 bor ? bit logical or bor c,src.b operation: operand operation summary bytes cycles c,mema.b logical-or carry with specified memory bit 2 2 c,memb.@l 2 2 c,@h+da.b 2 2 description: the specified bit of the source is logically ored with the carry flag bit value. the value of the source is unaffected. operand binary code operation notation c,mema.b * 1 1 1 1 0 1 1 0 c ? c or mema.b c,memb.@l 1 1 1 1 0 1 1 0 c ? c or [memb.7?2 + l.3?2]. [l.1?0] 0 1 0 0 a5 a4 a3 a2 c,@h+da.b 1 1 1 1 0 1 1 0 c ? c or [h + da.3?0].b 0 0 b1 b0 a3 a2 a1 a0 second byte bit addresses * mema.b 1 0 b1 b0 a3 a2 a1 a0 fb0h?fbfh 1 1 b1 b0 a3 a2 a1 a0 ff1h?ff9h examples: 1. the carry flag is logically ored with the p1.0 value: rcf ; c ? "0" bor c,p1.0 ; if p1.0 = "1", then c ? "1"; if p1.0 = "0", then c ? "0" 2. the p1 address is ff1h and register l contains the value 9h (1001b). the address (memb.7? 2) is 111100b and (l.3?2) = 10b. the resulting address is 11110010b or ff2h, specifying p2. the bit value for the bor instruction, (l.1?0) is 01b which specif ies bit 1. therefore, p1.@l = p2.1: ld l,#9h bor c,p1.@l ; p1.@l is specified as p2.1; c or p2.1
s3p7588x instructio n set 5- 37 bor ? bit logical or bor (continued) examples: 3. register h contains the value 2h and flag = 20h.3. the address of h is 0010b and flag(3?0) is 0000b. the resulting address is 00100000b or 20h. the bit value for the bor instruction is 3. therefore, @h+flag = 20h.3: flag equ 20h.3 ld h,#2h bor c,@h+flag ; c or flag (20h.3)
instruction set s3p 7588x 5- 38 btsf ? bit test and skip on false btsf dst.b operation: operand operation summary bytes cycles da.b test specified memory bit and skip if bit equals "0" 2 2 + s mema.b 2 2 + s memb.@l 2 2 + s @ h+da.b 2 2 + s description: the specified bit within the destination operand is tested. if it is a "0", the btsf instruction skips the instruction which immediately follows it; otherwise the instruction following the btsf is executed. the destination bit value is not affected. operand binary code operation notation da.b 1 1 b1 b0 0 0 1 0 skip if da.b = 0 a7 a6 a5 a4 a3 a2 a1 a0 mema.b * 1 1 1 1 1 0 0 0 skip if mema.b = 0 memb.@l 1 1 1 1 1 0 0 0 skip if [memb.7?2 + l.3-2]. [l.1?0] = 0 0 1 0 0 a5 a4 a3 a2 @h + da.b 1 1 1 1 1 0 0 0 skip if [h + da.3?0].b = 0 0 0 b1 b0 a3 a2 a1 a0 second byte bit addresses * mema.b 1 0 b1 b0 a3 a2 a1 a0 fb0h?fbfh 1 1 b1 b0 a3 a2 a1 a0 ff1h?ff9h examples: 1. if ram bit location 30h.2 is set to logic zero, the following instruction sequence will cause the program to continue exe cution from the instruction identifed as label2: btsf 30h.2 ; if 30h.2 = "0", then skip ret ; if 30h.2 = "1", return jp label2 2. you can use btsf in the same way to manipulate a port pin address bit: btsf p2.0 ; if p2.0 = "0", then skip ret ; if p2.0 = "1", then return jp label3
s3p7588x instructio n set 5- 39 btsf ? bit test and skip on false btsf (continued) examples: 3. p2.2, p2.3 and p3.0?p3.3 are tested: ld l,#0ah bp2 btsf p1.@l ; first, p1.@0ah = p2.2 ; (111100b) + 10b.10b = 0f2h.2 ret incs l jr bp2 4. bank 0, location 0a0h.0, is tested and (regardless of the current emb value) btsf has the following effect: flag equ 0a0h.0 ? ? ? bitr emb ? ? ? ld h,#0ah btsf @h+flag ; if bank 0 (ah + 0h).0 = 0a0h.0 = "0", then skip ret ? ? ?
instruction set s3p 7588x 5- 40 btst ? bit test and skip on true btst dst.b operation: operand operation summary bytes cycles c test carry bit and skip if set (= "1") 1 1 + s da.b test specified bit and skip if memory bit is set 2 2 + s mema.b 2 2 + s memb.@l 2 2 + s @ h+da.b 2 2 + s description: the specified bit within the destination operand is tested. if it is "1", the instruction that immediately follows the btst instruction is skipped; otherwise the instruction following the btst instruction is executed. the destination bit value is not affected. operand binary code operation notation c 1 1 0 1 0 1 1 1 skip if c = 1 da.b 1 1 b1 b0 0 0 1 1 skip if da.b = 1 a7 a6 a5 a4 a3 a2 a1 a0 mema.b * 1 1 1 1 1 0 0 1 skip if mema.b = 1 memb.@l 1 1 1 1 1 0 0 1 skip if [memb.7?2 + l.3?2]. [l.1?0] = 1 0 1 0 0 a5 a4 a3 a2 @ h+da.b 1 1 1 1 1 0 0 1 skip if [h + da.3?0].b = 1 0 0 b1 b0 a3 a2 a1 a0 second byte bit addresses * mema.b 1 0 b1 b0 a3 a2 a1 a0 fb0h?fbfh 1 1 b1 b0 a3 a2 a1 a0 ff1h?ff9h examples: 1. if ram bit location 30h.2 is set to logic zero, the following instruction sequence will execute the ret instruction: btst 30h.2 ; if 30h.2 = "1", then skip ret ; if 30h.2 = "0", return jp label2
s3p7588x instructio n set 5- 41 btst ? bit test and skip on true btst (continued) examples: 2. you can use btst in the same way to manipulate a port pin address bit: btst p2.0 ; if p2.0 = "1", then skip ret ; if p2.0 = "0", then return jp label3 3. assume that p2.2, p2.3 and p3.0?p3.3 are cleared to "0": ld l,#0ah bp2 btst p1.@l ; first, p1.@0ah = p2.2 (111100b) + 10b.10b = 0f2h.2 ret incs l jr bp2 4. bank 0, location 0a0h.0, is tested and (regardless of the current emb value) btst has t he following effect: flag equ 0a0h.0 ? ? ? bitr emb ? ? ? ld h,#0ah btst @h+flag ; if bank 0 (ah + 0h).0 = 0a0h.0 = "1", then skip ret ? ? ?
instruction set s3p 7588x 5- 42 btstz ? bit test and skip on true; clear bit btstz dst.b operation: operand operation summary bytes cycles mema.b test specified bit; skip and clear if memory bit is set 2 2 + s memb.@l 2 2 + s @ h+da.b 2 2 + s description: the specified bit within the destination operand is tested. if it is a "1", the instruction immediately following the btstz instruction is skipped; otherwise the instruction following the btstz is executed. the destination bit value is cleared. operand binary code operation notation mema.b * 1 1 1 1 1 1 0 1 skip if mema.b = 1 and clear memb.@l 1 1 1 1 1 1 0 1 skip if [memb.7?2 + l.3?2]. [l.1?0] = 1 and clear 0 1 0 0 a5 a4 a3 a2 @ h+da.b 1 1 1 1 1 1 0 1 skip if [h + da.3?0].b =1 and clear 0 0 b1 b0 a3 a2 a1 a0 second byte bit addresses * mema.b 1 0 b1 b0 a3 a2 a1 a0 fb0h?fbfh 1 1 b1 b0 a3 a2 a1 a0 ff1h?ff9h examples: 1. port pin p2.0 is toggled by checking the p2.0 value (level): btstz p2.0 ; if p2.0 = "1", then p2.0 ? "0" and skip bits p2.0 ; if p2.0 = "0", then p2.0 ? "1" jp label3 2. assume that port pins p2.2, p2.3 and p3.0?p3.3 are toggled: ld l,#0ah bp2 btstz p1.@l ; first, p1.@0ah = p2.2 ; (111100b) + 10b.10b = 0f2h.2 ret incs l jr bp2
s3p7588x instructio n set 5- 43 btstz ? bit test and skip on true; clear bit btstz (continued) examples: 3. bank 0, location 0a0h.0, is tested and emb = "0": flag equ 0a0h.0 ? ? ? bitr emb ? ? ? ld h,#0ah btstz @h+flag ; if bank 0 (ah + 0h).0 = 0a0h.0 = "1", clear and skip bits @h+flag ; if 0a0h.0 = "0", then 0a0h.0 ? "1"
instruction set s3p 7588x 5- 44 bxor ? bit exclusive or bxor c,src.b operation: operand operation summary bytes cycles c,mema.b exclusive-or carry with memory bit 2 2 c,memb.@l 2 2 c,@h+da.b 2 2 description: the specified bit of the source is logically xored with the carry bit value. the resultant bit is written to the carry flag. the source value is unaffected. operand binary code operation notation c,mema.b * 1 1 1 1 0 1 1 1 c ? c xor mema.b c,memb.@l 1 1 1 1 0 1 1 1 c ? c xor [memb.7?2 + l.3-2]. [l.1?0] 0 1 0 0 a5 a4 a3 a2 c,@h+da.b 1 1 1 1 0 1 1 1 c ? c xor [h + da.3?0].b 0 0 b1 b0 a3 a2 a1 a0 second byte bit addresses * mema.b 1 0 b1 b0 a3 a2 a1 a0 fb0h?fbfh 1 1 b1 b0 a3 a2 a1 a0 ff1h?ff9h examples: 1. the carry flag is logically xored with the p1.0 value: rcf ; c ? "0" bxor c,p1.0 ; if p1.0 = "1", then c ? "1"; if p1.0 = "0", then c ? "0" 2. the p1 address is ff1h and register l contains the value 9h (1001b). the a ddress (memb.7? 2) is 111100b and (l.3?2) = 10b. the resulting address is 11110010b or ff2h, specifying p2. the bit value for the bxor instruction, (l.1?0) is 01b which specifies bit 1. therefore, p1.@l = p2.1: ld l,#9h bxor c,p1.@l ; p1.@l is specified as p2.1; c xor p2.1
s3p7588x instructio n set 5- 45 bxor ? bit exclusive or bxor (continued) examples: 3. register h contains the value 2h and flag = 20h.3. the address of h is 0010b and flag(3?0) is 0000b. the resulting address is 00100000b or 20h. the bit value for the bor instruction is 3. therefore, @h+flag = 20h.3: flag equ 20h.3 ld h,#2h bxor c,@h+flag ; c xor flag (20h.3)
instruction set s3p 7588x 5- 46 call ? call procedure call dst operation: operand operation summary bytes cycles adr14 call direct in page (14 bits) 3 4 description: call calls a subroutine located at the destination address. the instruction adds three to the program counter to generate the return address and then pushes the result onto the stack, decreasing the stack pointer by six. the emb and erb are also pushed to the stack. program execution continues with the instruction at this address. the subroutine may therefore begin anywhere in the full 16 k byte program memory address space. operand binary code operation notation adr14 1 1 0 1 1 0 1 1 [(sp?1) (sp?2)] ? emb, erb 0 1 0 a12 a11 a10 a9 a8 [(sp?3) (sp?4)] ? pc7?0 a7 a6 a5 a4 a3 a2 a1 a0 [(sp?5) (sp?6)] ? pc12?8 example: the stack pointer value is 00h and the label 'play' is assigned to program memory location 0e3fh. executing the instruction call play at location 0123h will generate the following values: sp = 0fah 0ffh = 0h 0feh = emb, erb 0fdh = 2h 0fch = 6h 0fbh = 0h 0fah = 1h pc = 0e3fh data is written to stack locations 0ffh?0fah as follows: 0fah pc11 ? pc8 0fbh 0 0 0 pc12 0fch pc3 ? pc0 0fdh pc7 ? pc4 0feh 0 0 emb erb 0ffh 0 0 0 0
s3p7588x instructio n set 5- 47 calls ? call procedure ( short ) calls dst operation: operand operation summary bytes cycles adr11 call direct in page (11 bits) 2 3 description: the calls instruction unconditionally calls a subroutine located at the indicated address. the instruction increments the pc twice to obtain the address of the following instruction. then, it pushes the result onto the stack, decreasing the stack pointer six times. the higher bits of the pc, with the exception of the lower 11 bits, are cleared. the subroutine call must therefore be located within th e 2 k byte block (0000h?07ffh) of program memory. operand binary code operation notation adr11 1 1 1 0 1 a10 a9 a8 [(sp?1) (sp?2)] ? emb, erb a7 a6 a5 a4 a3 a2 a1 a0 [(sp?3) (sp?4)] ? pc7?0 [(sp?5) (sp?6)] ? pc10?8 example: the stack pointer value is 00h and the label 'play' is assigned to program memory location 0345h. executing the instruction calls play at location 0123h will generate the following val ues: sp = 0fah 0ffh = 0h 0feh = emb, erb 0fdh = 2h 0fch = 5h 0fbh = 0h 0fah = 1h pc = 0345h data is written to stack locations 0ffh?0fah as follows: 0fah 0 pc10 ? pc8 0fbh 0 0 0 0 0fch pc3 ? pc0 0fdh pc7 ? pc4 0feh 0 0 emb erb 0ffh 0 0 0 0
instruction set s3p 7588x 5- 48 ccf ? complement carry flag ccf operation: operand operation summary bytes cycles ? complement carry flag 1 1 description: the carry flag is complemented; if c = "1" it is changed to c = "0" and vice-versa. operand binary code operation notation ? 1 1 0 1 0 1 1 0 c ? c example: if the carry flag is logic zero, the instruction ccf changes the value to logic one.
s3p7588x instructio n set 5- 49 com ? complement accumulator com a operation: operand operation summary bytes cycles a complement accumulator (a) 2 2 description: the accumulator value is complemented; if the bit value of a is "1", it is changed to "0" and vice versa. operand binary code operation notation a 1 1 0 1 1 1 0 1 a ? a 0 0 1 1 1 1 1 1 example: if the accumulator contains the value 4h (0100b), the instruction com a leaves the value 0bh (1011b) in the accumulator.
instruction set s3p 7588x 5- 50 cpse ? compare and skip if equal cpse dst,src operation: operand operation summary bytes cycles r,#im compare and skip if register equals # im 2 2 + s @ hl,#im compare and skip if indirect data memory equals # im 2 2 + s a,r compare and skip if a equals r 2 2 + s a,@hl compare and skip if a equals indirect data memory 1 1 + s ea,@hl compare and skip if ea equals indirect data memory 2 2 + s ea,rr compare and skip if ea equals rr 2 2 + s description: cpse compares the source operand (subtracts it from) the destination operand, and skips the next instruction if the values are equal. neither operand is affected by the comparison. operand binary code operation notation r,#im 1 1 0 1 1 0 0 1 skip if r = im d3 d2 d1 d0 0 r2 r1 r0 @ hl,#im 1 1 0 1 1 1 0 1 skip if (hl) = im 0 1 1 1 d3 d2 d1 d0 a,r 1 1 0 1 1 1 0 1 skip if a = r 0 1 1 0 1 r2 r1 r0 a,@hl 0 0 1 1 1 0 0 0 skip if a = (hl) ea,@hl 1 1 0 1 1 1 0 0 skip if a = (hl), e = (hl+1) 0 0 0 0 1 0 0 1 ea,rr 1 1 0 1 1 1 0 0 skip if ea = rr 1 1 1 0 1 r2 r1 0 example: the extended accumulator contains the value 34h and register pair hl contains 56h. the second instruction (ret) in the instruction sequence cpse ea,hl ret is not skipped. that is, the subroutine returns since the result of the comparison is 'not equal.'
s3p7588x instructio n set 5- 51 decs ? decrement and skip on borrow decs dst operation: operand operation summary bytes cycles r decrement register (r); skip on borrow 1 1 + s rr decrement register pair (rr); skip on borrow 2 2 + s description: the destination is decremented by one. an original value of 00h will underflow to 0ffh. if a borrow occurs, a skip is executed. the carry flag value is unaffected. operand binary code operation notation r 0 1 0 0 1 r2 r1 r0 r ? r?1; skip on borrow rr 1 1 0 1 1 1 0 0 rr ? rr?1; skip on borrow 1 1 0 1 1 r2 r1 0 examples: 1. register pair hl contains the value 7fh (01111111b). the following instruction leaves the value 7eh in register pair hl: decs hl 2. register a contains the value 0h. the following instruction sequence leaves the value 0ffh in register a. since a "borrow" occurs, the 'call play1' instruction is skipped and the 'call play2' instruction is executed: decs a ; "borrow" occurs cal l play1 ; skipped call play2 ; executed
instruction set s3p 7588x 5- 52 di ? disable interrupts di operation: operand operation summary bytes cycles ? disable all interrupts 2 2 description: bit 3 of the interrupt priority register ipr, ime, is cleared to logic zero, disabling all interrupts. interrupts can still set their respective interrupt status latches, but the cpu will not directly service them. operand binary code operation notation ? 1 1 1 1 1 1 1 0 ime ? 0 1 0 1 1 0 0 1 0 example: if the ime bit (bit 3 of the ipr) is logic one (e.g., all instructions are enabled), the instruction di sets the ime bit to logic zero, disabling all interrupts.
s3p7588x instructio n set 5- 53 ei ? enable interrupts ei operation: operand operation summary bytes cycles ? enable all interrupts 2 2 description: bit 3 of the interrupt priority register ipr (ime) is set to logic one. this allows all interrupts to be serviced when they occur, assuming they are enabled. if an interrupt's status lat ch was previously enabled by an interrupt, this interrupt can also be serviced. operand binary code operation notation ? 1 1 1 1 1 1 1 1 im ? 1 1 0 1 1 0 0 1 0 example: if the ime bit (bit 3 of the ipr) is logic zero (e.g., all instructions are disabled), the instruction ei sets the ime bit to logic one, enabling all interrupts.
instruction set s3p 7588x 5- 54 idle ? idle operation idle operation: operand operation summary bytes cycles ? engage cpu idle mode 2 2 description: idle causes the cpu clock to stop while the system clock continues oscillating by setting bit 2 of the power control register (pcon). after an idle instruction has been executed, peripheral hard ware remains operative. in application programs, an idle instruction should be immediately followed by at least three nop instructions. this ensures an adequate time interval for the clock to stabilize before the next instruction is executed. operand binary code operation notation ? 1 1 1 1 1 1 1 1 pcon.2 ? 1 1 0 1 0 0 0 1 1 example: the instruction sequence idle nop nop nop sets bit 2 of the pcon register to logic one, stopping the cpu clock. the three nop instructions provide the necessary timing delay for clock stabilization before the next instruction in the program sequence is executed.
s3p7588x instructio n set 5- 55 incs ? increment and skip on carry incs dst operation: operand operation summary bytes cycles r increment register (r); skip on carry 1 1 + s da increment direct data memory; skip on carry 2 2 + s @hl increment indirect data memory; skip on carry 2 2 + s rrb increment register pair ( rrb); skip on carry 1 1 + s description: the instruction incs increments the value of the destination operand by one. an original value of 0fh will, for example, overflow to 00h. if a carry occurs, the next instruction is skipped. the carry flag value is unaffected. operand binary code operation notation r 0 1 0 1 1 r2 r1 r0 r ? r + 1; skip on carry da 1 1 0 0 1 0 1 0 da ? da + 1; skip on carry a7 a6 a5 a4 a3 a2 a1 a0 @hl 1 1 0 1 1 1 0 1 (hl) ? (hl) + 1; skip on carry 0 1 1 0 0 0 1 0 rrb 1 0 0 0 0 r2 r1 0 rrb ? rrb + 1; skip on carry example: register pair hl contains the value 7eh (01111110b). ram location 7eh contains 0fh. the instruction sequence incs @hl ; 7eh ? "0" incs hl ; skip incs @hl ; 7eh ? "1" leaves the register pair hl with the value 7eh and ram location 7eh with the value 1h. since a carry occurred, the second instruction is skipped. the carry flag value remains unchanged.
instruction set s3p 7588x 5- 56 iret ? return from interrupt iret operation: operand operation summary bytes cycles ? return from interrupt 1 3 description: iret is used at the end of an interrupt service routine. it pops the pc values successively from the stack and restores the m to the program counter. the stack pointer is incremented by six and the psw, enable memory bank (emb) bit, and enable register bank (erb) bit are also automatically restored to their pre-interrupt values. program execution continues from the resulting address, which is generally the instruction immediately after the point at which the interrupt request was detected. if a lower-level or same-level interrupt was pending when the iret was executed, iret will be executed before the pending interrupt is processed. since the 'a14' bit of an interrupt return address is not stored in the stack, this bit location is always interpreted as a logic zero. the start address in the rom must for this reason be 3fffh. operand binary code operation notation ? 1 1 0 1 0 1 0 1 pc12?8 ? (sp + 1) (sp) pc7?0 ? sp + 2) (sp + 3) psw ? (sp + 4) (sp + 5) sp ? sp + 6 example: the stack pointer contains the value 0fah. an interrupt is detected in the instruction at location 0122h. ram locations 0fdh, 0fch, and 0fah contain the values 2h, 3h, and 1h, respectively. the instruction iret leaves the stack pointer with the value 00h and the program returns to continue execution at location 123h. during a return from interrupt, data is popped from the stack to the program counter. the data in stack locations 0ffh?0fah is organized as follows: 0fah pc11 ? pc8 0fbh 0 0 0 pc12 0fch pc3 ? pc0 0fdh pc7 ? pc4 0feh is1 is0 emb erb 0ffh c sc2 sc1 sc0
s3p7588x instructio n set 5- 57 jp ? jump jp dst operation: operand operation summary bytes cycles adr14 jump to direct address (14 bits) 3 3 description: jp causes an unconditional branch to the indicated address by replacing the contents of the program counter with the address specified in the destination operand. the destination can be anywhere in the 16 k byte program memory address space. operand binary code operation notation adr14 1 1 0 1 1 0 1 1 pc12?0 ? adr14 0 0 0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 example: the label 'syscon' is assigned to the instruction at program location 07ffh. the instruction jp syscon at location 0123h will load the program counter with the value 07ffh.
instruction set s3p 7588x 5- 58 jps ? jump ( short ) jps dst operation: operand operation summary bytes cycles adr12 jump direct in page (12 bits) 2 2 description: jps causes an unconditional branch to the indicated address with the 4 k byte program memory address space. bits 0?11 of the program counter are replaced with the directly specified address. the destination address for this jump is specified to the assembler by a label or by an actual address in program memory. operand binary code operation notation adr12 1 0 0 1 a11 a10 a9 a8 pc12?0 ? pc12+ adr11?0 a7 a6 a5 a4 a3 a2 a1 a0 example: the label 'sub' is assigned to the instruction at program memory location 00ffh. the instruction jps sub at location 0eabh will load the program counter with the value 00ffh. normally, the jps instruction jumps to the address in the block in which the instruction is located. if the first byte of the instruction code is located at address xffeh or xfffh, the instruction will jump to the next block. if the instruction ' jps sub' were located instead at program memory address 0ffeh or 0fffh, the instruction ' jps sub' would load the pc with the value 10ffh, causing a program malfunction.
s3p7588x instructio n set 5- 59 jr ? jump relative ( very short ) jr dst operation: operand operation summary bytes cycles # im branch to relative immediate address 1 2 @wx branch relative to contents of wx register 2 3 @ea branch relative to contents of ea 2 3 description: jr causes the relative address to be added to the program counter and passes control to the instruction whose address is now in the pc. the range of the relative address is current pc ? 15 to current pc + 16. the destination address for this jump is specified to the assembler by a label, an actual address, or by immediate data using a plus sign (+) or a minus sign (?). for immediate addressing, the (+) range is from 2 to 16 and the (?) range is from ?1 to ?15. if a 0, 1, or any other number that is outside these ranges are used, the assembler interprets it as an error. for jr @wx and jr @ea branch relative instructions, the valid range for the relative address is 0h?0ffh. the destination address for these jumps can be specified to the assembler by a label that lies anywhere within the current 256-byte block. normally, the 'jr @wx' and 'jr @ea' instructions jump to the address in the page in which the instruction is located. however, if the first byte of the instruction code is located at address xxfeh or xxffh, the instruction will jump to the next page. operand binary code operation notation # im * pc12?0 ? adr (pc?15 to pc+16) @wx 1 1 0 1 1 1 0 1 pc12?0 ? pc12?8 + (wx) 0 1 1 0 0 1 0 0 @ea 1 1 0 1 1 1 0 1 pc12?0 ? pc12?8 + (ea) 0 1 1 0 0 0 0 0 first byte condition * jr # im 0 0 0 1 a3 a2 a1 a0 pc ? pc+2 to pc+16 0 0 0 0 a3 a2 a1 a0 pc ? pc?1 to pc?15
instruction set s3p 7588x 5- 60 jr ? jump relative (very short ) jr (continued) examples: 1. a short form for a relative jump to label 'kk' is the instruction jr kk where 'kk' must be within the allowed range of curre nt pc?15 to current pc+16. the jr instruction has in this case the effect of an unconditional jp instruction. 2. in the following instruction sequence, if the instruction 'ld wx, #02h' were to be executed in place of 'ld wx,#00h', the program would jump to 1002h and ' jps bbb' would be executed. if 'ld ea,#04h' were to be executed, the jump would be to1004h and ' jps ccc' would be executed. org 1000h jps aaa jps bbb jps ccc jps ddd ld wx,#00h ; wx ? 00h ld ea,wx ads wx,ea ; wx ? (wx) + (wx) jr @wx ; current pc12?8 (10h) + wx (00h) = 1000h ; jump to address 1000h and execute jps aaa 3. here is another example: org 1100h ld a,#0h ld a,#1h ld a,#2h ld a,#3h ld 30h,a ; address 30h ? a jps yyy xxx ld ea,#00h ; ea ? 00h jr @ea ; jump to address 1100h ; address 30h ? 00h if 'ld ea,#01h' were to be ex ecuted in place of 'ld ea,#00h', the program would jump to 1001h and address 30h would contain the value 1h. if 'ld ea,#02h' were to be executed, the jump would be to 1002h and address 30h would contain the value 2h.
s3p7588x instructio n set 5- 61 ld ? load ld dst,src operation: operand operation summary bytes cycles a,#im load 4-bit immediate data to a 1 1 a,@rra load indirect data memory contents to a 1 1 a,da load direct data memory contents to a 2 2 a,ra load register contents to a 2 2 ra,#im load 4-bit immediate data to register 2 2 rr,#imm load 8-bit immediate data to register 2 2 da,a load contents of a to direct data memory 2 2 ra,a load contents of a to register 2 2 ea,@hl load indirect data memory contents to ea 2 2 ea,da load direct data memory contents to ea 2 2 ea,rrb load register contents to ea 2 2 @hl,a load contents of a to indirect data memory 1 1 da,ea load contents of ea to data memory 2 2 rrb,ea load contents of ea to register 2 2 @hl,ea load contents of ea to indirect data memory 2 2 description: the contents of the source are loaded into the destination. the source's contents are unaffected. if an instruction such as 'ld a,#im' (ld ea,#imm) or 'ld hl,#imm' is written more than two times in succession, only the first ld will be executed; the other similar instructions that immediately follow the first ld will be treated like a nop. this is called the 'redundancy effect' (see examples below). operand binary code operation notation a,#im 1 0 1 1 d3 d2 d1 d0 a ? im a,@rra 1 0 0 0 1 i2 i1 i0 a ? ( rra) a,da 1 0 0 0 1 1 0 0 a ? da a7 a6 a5 a4 a3 a2 a1 a0 a,ra 1 1 0 1 1 1 0 1 a ? ra 0 0 0 0 1 r2 r1 r0 ra,#im 1 1 0 1 1 0 0 1 ra ? im d3 d2 d1 d0 1 r2 r1 r0
instruction set s3p 7588x 5- 62 ld ? l oad ld (continued) description: operand binary code operation notation rr,#imm 1 0 0 0 0 r2 r1 1 rr ? imm d7 d6 d5 d4 d3 d2 d1 d0 da,a 1 0 0 0 1 0 0 1 da ? a a7 a6 a5 a4 a3 a2 a1 a0 ra,a 1 1 0 1 1 1 0 1 ra ? a 0 0 0 0 0 r2 r1 r0 ea,@hl 1 1 0 1 1 1 0 0 a ? (hl), e ? (hl + 1) 0 0 0 0 1 0 0 0 ea,da 1 1 0 0 1 1 1 0 a ? da, e ? da + 1 a7 a6 a5 a4 a3 a2 a1 a0 ea,rrb 1 1 0 1 1 1 0 0 ea ? rrb 1 1 1 1 1 r2 r1 0 @hl,a 1 1 0 0 0 1 0 0 (hl) ? a da,ea 1 1 0 0 1 1 0 1 da ? a, da + 1 ? e a7 a6 a5 a4 a3 a2 a1 a0 rrb,ea 1 1 0 1 1 1 0 0 rrb ? ea 1 1 1 1 0 r2 r1 0 @hl,ea 1 1 0 1 1 1 0 0 (hl) ? a, (hl + 1) ? e 0 0 0 0 0 0 0 0 examples: 1. ram location 30h contains the value 4h. the ram location values are 40h, 41h and 0ah, 3h respectively. the following instruction sequence leaves the value 40h in point pair hl, 0ah in the accumulator and in ram location 40h, and 3h in register e. ld hl,#30h ; hl ? 30h ld a,@hl ; a ? 4h ld hl,#40h ; hl ? 40h ld ea,@hl ; a ? 0ah, e ? 3h ld @hl,a ; ram (40h) ? 0ah
s3p7588x instructio n set 5- 63 ld ? load ld (continued) examples: 2. if an instruction such as ld a,#im (ld ea,#imm) or ld hl,#imm is written more than two times in succession, only the first ld is executed; the next instructions are treated as nops. here are two examples of this 'redundancy effect': ld a,#1h ; a ? 1h ld ea,#2h ; nop ld a,#3h ; nop ld 23h,a ; (23h) ? 1h ld hl,#10h ; hl ? 10h ld hl,#20h ; nop ld a,#3h ; a ? 3h ld ea,#35 ; nop ld @hl,a ; (10h) ? 3h the following table contains descriptions of special characteristics of the ld instruction when used in different addressing modes: instruction operation description and guidelines ld a,#im since the 'redundancy effect' occurs with instructions like ld ea,#imm, if this instruction is used consecutively, the second and additional instructions of the same type will be treated like nops. ld a,@rra load the data memory contents pointed to by 8-bit rra register pairs (hl, wx, wl) to the a register. ld a,da load direct data memory contents to the a register. ld a,ra load 4-bit register ra (e, l, h, x, w, z, y) to the a register. ld ra,#im load 4-bit immediate data into the ra register (e, l, h, x, w, y, z). ld rr,#imm load 8-bit immediate data into the ra register (ea, hl, wx, yz). there is a redundancy effect if the operation addresses the hl or ea registers. ld da,a load contents of register a to direct data memory address. ld ra,a load contents of register a to 4-bit ra register (e, l, h, x, w, z, y).
instruction set s3p 7588x 5- 64 ld ? load ld (concluded) examples: instruction operation description and guidelines ld ea,@hl load data memory contents pointed to by 8-bit register hl to the a register, and the contents of hl+1 to the e register. the contents of register l must be an even number. if the number is odd, the lsb of register l is recognized as a logic zero (an even number), and it is not replaced with the true value. for example, 'ld hl,#36h' loads immediate 36h to hl and the next instruction 'ld ea,@hl' loads the contents of 36h to register a and the contents of 37h to register e. ld ea,da load direct data memory contents of da to the a register, and the next direct data memory contents of da + 1 to the e register. the da value must be an even number. if it is an odd number, the lsb of da is recognized as a logic zero (an even number), and it is not replaced with the true value. for example, 'ld ea,37h' loads the contents of 36h to the a register and the contents of 37h to the e register. ld ea,rrb load 8-bit rrb register (hl, wx, yz) to the ea register. h, w, and y register values are loaded into the e register, and the l, x, and z values into the a register. ld @hl,a load a register contents to data memory location pointed to by the 8-bit hl register value. ld da,ea load the a register contents to direct data memory and the e register contents to the next direct data memory location. the da value must be an even number. if it is an odd number, the lsb of the da value is recognized as logic zero (an even number), and is not replaced with the true value. ld rrb,ea load contents of ea to the 8-bit rrb register (hl, wx, yz). the e register is loaded into the h, w, and y register and the a register into the l, x, and z register. ld @hl,ea load the a register to data memory location pointed to by the 8-bit hl register, and the e register contents to the next location, hl + 1. the contents of the l register must be an even number. if the number is odd, the lsb of the l register is recognized as logic zero (an even number), and is not replaced with the true value. for example, 'ld hl,#36h' loads immediate 36h to register hl; the instruction 'ld @hl,ea' loads the contents of a into address 36h and the contents of e into address 37h.
s3p7588x instructio n set 5- 65 ldb ? load bit ldb dst,src.b ldb dst.b,src operation: operand operation summary bytes cycles mema.b,c load carry bit to a specified memory bit 2 2 memb.@l,c load carry bit to a specified indirect memory bit 2 2 @ h+da.b,c 2 2 c,mema.b load memory bit to a specified carry bit 2 2 c,memb.@l load indirect memory bit to a specified carry bit 2 2 c,@h+da.b 2 2 description: the boolean variable indicated by the first or second operand is copied into the location specified by the second or first operand. one of the operands must be the carry flag; the other may be any di rectly or indirectly addressable bit. the source is unaffected. operand binary code operation notation mema.b,c * 1 1 1 1 1 1 0 0 mema.b ? c memb.@l,c 1 1 1 1 1 1 0 0 memb.7?2 + [l.3?2]. [l.1?0] ? c 0 1 0 0 a5 a4 a3 a2 @ h+da.b,c 1 1 1 1 1 1 0 0 h + [da.3?0].b ? (c) 0 b2 b1 b0 a3 a2 a1 a0 c,mema.b* 1 1 1 1 0 1 0 0 c ? mema.b c,memb.@l 1 1 1 1 0 1 0 0 c ? memb.7?2 + [l.3?2] . [l.1?0] 0 1 0 0 a5 a4 a3 a2 c,@h+da.b 1 1 1 1 0 1 0 0 c ? [h + da.3?0].b 0 b2 b1 b0 a3 a2 a1 a0 second byte bit addresses * mema.b 1 0 b1 b0 a3 a2 a1 a0 fb0h?fbfh 1 1 b1 b0 a3 a2 a1 a0 ff1h?ff9h
instruction set s3p 7588x 5- 66 ldb ? load bit ldb (continued) examples: 1. the carry flag is set and the data value at input pin p1.0 is logic zero. the following instruction clears the carry flag to logic zero. ldb c,p1 .0 2. the p1 address is ff1h and the l register contains the value 9h (1001b). the address (memb.7?2) is 111100b and (l.3?2) is 10b. the resulting address is 11110010b or ff2h and p2 is addressed. the bit value (l.1?0) is specified as 01b (bit 1). ld l,#9h ldb c,p1.@l ; p1.@l specifies p2.1 and c ? p2.1 3. the h register contains the value 2h and flag = 20h.3. the address for h is 0010b and for flag(3?0) the address is 0000b. the resulting address is 00100000b or 20h. the bit value is 3. therefore, @h+flag = 20h.3. flag equ 20h.3 ld h,#2h ldb c,@h+flag ; c ? flag (20h.3) 4. the following instruction sequence sets the carry flag and the loads the "1" data value to the output pin p2.0, setting it to output mode: scf ; c ? "1" ldb p2.0,c ; p2.0 ? "1" 5. the p1 address is ff1h and l = 9h (1001b). the address (memb.7?2) is 111100b and (l.3? 2) is 10 b. the resulting address, 11110010b specifies p2. the bit value (l.1?0) is specified as 01b (bit 1). therefore, p1.@l = p2.1. scf ; c ? "1" ld l,#9h ldb p1.@l,c ; p1.@l specifies p2.1 ; p2.1 ? "1" 6. in this example, h = 2h and flag = 20h.3 and the address 20h is specified. since the bit value is 3, @h+flag = 20h.3: flag equ 20h.3 rcf ; c ? "0" ld h,#2h ldb @h+flag,c ; flag(20h.3) ? "0" note: port pin names used in examples 4 and 5 may vary with different devices.
s3p7588x instructio n set 5- 67 ldc ? load code byte ldc dst,src operation: operand operation summary bytes cycles ea,@wx load code byte from wx to ea 1 3 ea,@ea load code byte from ea to ea 1 3 description: this instruction is used to load a byte from program memory into an extended accumulator. the address of the byte fetched is the five highest bit values in the program counter and the conten ts of an 8-bit working register (either wx or ea). the contents of the source are unaffected. operand binary code operation notation ea,@wx 1 1 0 0 1 1 0 0 ea ? [pc12?8 + (wx)] ea,@ea 1 1 0 0 1 0 0 0 ea ? [pc12?8 + (ea)] examples: 1. the following instructions will load one of four values defined by the define byte ( db) directive to the extended accumulator: ld ea,#00h call display jps main org 0500h db 66h db 77h db 8 8h db 99h ? ? ? display ldc ea,@ea ; ea ? address 0500h = 66h ret if the instruction 'ld ea,#01h' is executed in place of 'ld ea,#00h', the content of 0501h (77h) is loaded to the ea register. if 'ld ea,#02h' is executed, the content of address 0502h (88h) is loaded to ea.
instruction set s3p 7588x 5- 68 ldc ? load code byte ldc (continued) examples: 2. the following instructions will load one of four values defined by the define byte ( db) directive to the extended accumulator: org 0500 db 66h db 77h db 88h db 99h ? ? ? display ld wx,#00h ldc ea,@wx ; ea ? address 0500h = 66h ret if the instruction 'ld wx,#01h' is executed in place of 'ld wx,#00h', then ea ? address 0501h = 77h. if the instruction 'ld wx,#02h' is executed in place of 'ld wx,#00h', then ea ? address 0502h = 88h. 3. normally, the ldc ea, @ea and the ldc ea, @wx instructions r eference the table data on the page on which the instruction is located. if, however, the instruction is located at address xxffh, it will reference table data on the next page. in this example, the upper 4 bits of the address at location 0200h is loaded into register e and the lower 4 bits into register a: org 01fdh 01fdh ld wx,#00h 01ffh ldc ea,@wx ; e ? upper 4 bits of 0200h address ; a ? lower 4 bits of 0200h address 4. here is another example of page referencing with the ldc instruction: org 0100 db 67h smb 0 ld hl,#30h ; even number ld wx,#00h ldc ea,@wx ; e ? upper 4 bits of 0100h address ; a ? lower 4 bits of 0100h address ld @hl,ea ; ram (30h) ? 7, ram (31h) ? 6
s3p7588x instructio n set 5- 69 ldd ? load data memory and decrement ldd dst operation: operand operation summary bytes cycles a,@hl load indirect data memory contents to a; decrement register l contents and skip on borrow 1 2 + s description: the contents of a data memory location are loaded into the accumulator, and the contents of the register l are decreased by one. if a "borrow" occurs (e.g., if the resulting value in register l is 0fh), the next instruction is skipped. the contents of data memory and the carry flag value are not affected. operand binary code operation notation a,@hl 1 0 0 0 1 0 1 1 a ? (hl), then l ? l?1; skip if l = 0fh example: in this example, assume that register pair hl contains 20h and internal ram location 20h contains the value 0fh: ld hl,#20h ldd a,@hl ; a ? (hl) and l ? l?1 jps xxx ; skip jps yyy ; h ? 2h and l ? 0fh the instruction ' jps xxx' is skipped since a "borrow" occurred after the 'ldd a,@hl' and instruction ' jps yyy' is executed.
instruction set s3p 7588x 5- 70 ldi ? load data memory and increment ldi dst,src operation: operand operation summary bytes cycles a,@hl load indirect data memory to a; increment register l contents and skip on overflow 1 2 + s description: the contents of a data memory location are loaded into the accumulator, and the contents of the register l are incremented by one. if an overflow occurs (e.g., if the resulting value in register l is 0h), the next instruct ion is skipped. the contents of data memory and the carry flag value are not affected. operand binary code operation notation a,@hl 1 0 0 0 1 0 1 0 a ? (hl), then l ? l+1; skip if l = 0h example: assume that register pair hl contains the address 2fh and internal ram location 2fh con tains the value 0fh: ld hl,#2fh ldi a,@hl ; a ? (hl) and l ? l+1 jps xxx ; skip jps yyy ; h ? 2h and l ? 0h the instruction ' jps xxx' is skipped since an overflow occurred after the 'ldi a,@hl' and the instruction ' jps yyy' is executed.
s3p7588x instructio n set 5- 71 nop ? no operation nop operation: operand operation summary bytes cycles ? no operation 1 1 description: no operation is performed by a nop instruction. it is typically used for timing delays. one nop causes a 1-cycle delay: with a 1 s cycle time, five nops would therefore cause a 5 s delay. program execution continues with the instruction immediately following the nop. only the pc is affected. at least three nop instructions should follow a stop or idle instruction. operand binary code operation notation ? 1 0 1 0 0 0 0 0 no operation example: three nop instructions follow the stop instruction to provide a short interval for clock stabilization before power-down mode is initiated: stop nop nop nop
instruction set s3p 7588x 5- 72 or ? logical or or dst,src operation: operand operation summary bytes cycles a, # im logical-or immediate data to a 2 2 a, @hl logical-or indirect data memory contents to a 1 1 ea,rr logical-or double register to ea 2 2 rrb,ea logical-or ea to double register 2 2 description: the source operand is logically ored with the destination operand. the result is stored in the destination. the contents of the source are unaffected. operand binary code operation notation a, # im 1 1 0 1 1 1 0 1 a ? a or im 0 0 1 0 d3 d2 d1 d0 a, @hl 0 0 1 1 1 0 1 0 a ? a or (hl) ea,rr 1 1 0 1 1 1 0 0 ea ? ea or rr 0 0 1 0 1 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 rrb ? rrb or ea 0 0 1 0 0 r2 r1 0 example: if the accumulator contains the value 0c3h (11000011b) and register pair hl the value 55h (01010101b), the instruction or ea,@hl leaves the value 0d7h (11010111b) in the accumulator .
s3p7588x instructio n set 5- 73 pop ? pop from stack pop dst operation: operand operation summary bytes cycles rr pop to register pair from stack 1 1 sb pop smb and srb values from stack 2 2 description: the contents of the ram location addressed by the stack pointer is read, and the sp is incremented by two. the value read is then transferred to the variable indicated by the destination operand. operand binary code operation notation rr 0 0 1 0 1 r2 r1 0 rr l ? (sp), rr h ? (sp+1) sp ? sp+2 sb 1 1 0 1 1 1 0 1 (srb) ? (sp), smb ? (sp+1), sp ? sp+2 0 1 1 0 0 1 1 0 example: the sp value is equal to 0edh, and ram locations 0efh through 0edh contain the values 2h, 3h, and 4h, respectively. the instruction pop hl leaves the stack pointer set to 0efh and the data pointer pair hl set to 34h.
instruction set s3p 7588x 5- 74 push ? push onto stack push src operation: operand operation summary bytes cycles rr push register pair onto stack 1 1 sb push smb and srb values onto stack 2 2 description: the sp is then decreased by two and the contents of the source operand are copied into the ram location addressed by the stack pointer, thereby adding a new element to the top of the stack. operand binary code operation notation rr 0 0 1 0 1 r2 r1 1 (sp?1) ? rr h , (sp?2) ? rr l sp ? sp?2 sb 1 1 0 1 1 1 0 1 (sp?1) ? smb, (sp?2) ? srb; (sp) ? sp?2 0 1 1 0 0 1 1 1 example: as an interrupt service routine begins, the stack pointer contains the value 0fah and the data pointer register pair hl contains the value 20h. the instruction push hl leaves the stack pointer set to 0f8h and stores the values 2h and 0h in ram locations 0f9h and 0f8h, respectively.
s3p7588x instructio n set 5- 75 rcf ? reset carry flag rcf operation: operand operation summary bytes cycles ? reset carry flag to logic zero 1 1 description: the carry flag is cleared to logic zero, regardless of its previous value. operand binary code operation notation ? 1 1 1 0 0 1 1 0 c ? 0 example: assuming the carry flag is set to logic one, the instruction rcf resets (clears) the carry flag to logic zero.
instruction set s3p 7588x 5- 76 ref ? reference instruction ref dst operation: operand operation summary bytes cycles memc reference code 1 3 * * the ref instruction for a 16k call instruction is 4 cycles. description: the ref instruction is used to rewrite into 1-byte form, arbitrary 2-byte or 3-byte instructions (or two 1-byte instructions) stored in the ref instruction reference area in program memory. ref reduces the number of program memory accesses for a program. operand binary code operation notation memc t7 t6 t5 t4 t3 t2 t1 t0 pc12?0 = memc7?4, memc3?0 <1 tjp and tcall are 2-byte p seudo-instructions that are used only to specify the reference area: 1. when the reference area is specified by the tjp instruction, memc.7?6 = 00 pc11?0 ? memc.3?0 + ( memc + 1) 2. when the reference area is specified by the tcall instruction, memc.7?6 = 01 (sp?4) (sp?1) (sp?2) ? pc11?0 sp?3 ? emb, erb, 0, 0 pc11?0 ? memc.3?0 + ( memc + 1) sp ? sp?4 when the reference area is specified by any other instruction, the ' memc' and ' memc + 1' instructions are executed. instructions referenced by ref occupy 2 bytes of memory space (for two 1-byte instructions or one 2-byte instruction) and must be written as an even number from 0020h to 007fh in rom. in addition, the destination address of the tjp and tcall instructions must be located with the 3fffh address. tjp and tcall are reference instructions for jp/jps and call/calls. if the inst ruction following a ref is subject to the 'redundancy effect', the redundant instruction is skipped. if, however, the ref follows a redundant instruction, it is executed. on the other hand, the binary code of a ref instruction is 1 byte. the upper 4 bits become the higher address bits of the referenced instruction, and the lower 4 bits of the referenced instruction ( x 1/2) becomes the lower address, producing a total of 8 bits or 1 byte (see example 3 below).
s3p7588x instructio n set 5- 77 ref ? reference instruction ref (continued) examples: 1. instructions can be executed efficiently using ref, as shown in the following example: org 0020h aaa ld hl,#00h bbb ld ea,#ffh ccc tcall sub1 ddd tjp sub2 ? ? ? org 0080h ref aaa ; ld hl,#00h ref bbb ; ld ea,#ffh ref ccc ; call sub1 ref ddd ; jp sub2 2. the following example shows how the ref instruction is executed in relation to ld instructions that have a 'redundancy effect': org 0020h aaa ld ea,#40h ? ? ? org 0100h ld ea,#30h r ef aaa ; not skipped ? ? ? ref aaa ld ea,#50h ; skipped srb 2
instruction set s3p 7588x 5- 78 ref ? reference instruction ref (concluded) examples: 3. in this example the binary code of 'ref a1' at locations 20h?21h is 20h, for 'ref a2' at locations 22h?23h, it is 21h, and for 'ref a3' at 24h?25h, the binary code is 22h : opcode symbol instruction org 0020h 83 00 a1 ld hl,#00h 83 03 a2 ld hl,#03h 83 05 a3 ld hl,#05h 83 10 a4 ld hl,#10h 83 26 a5 ld hl,#26h 83 08 a6 ld hl,#08h 83 0f a7 ld hl,# 0fh 83 f0 a8 ld hl,#0f0h 83 67 a9 ld hl,#067h 41 0b a10 tcall sub1 01 0d a11 tjp sub2 ? ? ? org 0100h 20 ref a1 ; ld hl,#00h 21 ref a2 ; ld hl,#03h 22 ref a3 ; ld hl,#05h 23 ref a4 ; ld hl,#10h 24 ref a5 ; ld hl,#26h 25 ref a6 ; ld hl,#08h 26 ref a7 ; ld hl,#0fh 27 ref a8 ; ld hl,#0f0h 30 ref a9 ; ld hl,#067h 31 ref a10 ; call sub1 32 ref a11 ; jp sub2
s3p7588x instructio n set 5- 79 ret ? return from subroutine ret operation: operand operation summary bytes cycles ? return from subroutine 1 3 description: ret pops the pc values successively from the stack, incrementing the stack pointer by six. program execution continues from the resulting address, generally the instruction immediately following a call or calls. operand binary code operation notation ? 1 1 0 0 0 1 0 1 pc12?8 ? (sp+1) (sp) pc7?0 ? (sp+2) (sp+3) psw ? emb,erb sp ? sp+6 example: the stack pointer contains the value 0fah. ram locations 0fah, 0fbh, 0fch, and and 0fdh contain 1h, 0h, 5h, and 2h, respectively. the instruction ret leaves the stack pointer with the new value of 00h and program execution continues from location 0125h. during a return from subroutine, pc values are popped from stack locations as follows: sp ? pc11 ? pc8 sp + 1 0 0 0 pc12 sp + 2 pc3 ? pc0 sp + 3 pc7 ? pc4 sp + 4 0 0 emb erb sp + 5 0 0 0 0 sp + 6
instruction set s3p 7588x 5- 80 rrc ? rotate accumulator right through carry rrc a operation: operand operation summary bytes cycles a rotate right through carry bit 1 1 description: the four bits in the accumulator and the carry flag are together rotated one bit to the right. bit 0 moves into the carry flag and the original carry value moves into the bit 3 accumulator position. operand binary code operation notation a 1 0 0 0 1 0 0 0 c ? a.0, a3 ? c a.n?1 ? a.n (n = 1, 2, 3) example: the accumulator contains the value 5h (0101b) and the carry flag is cleared to logic zero. the instruction rrc a leaves the accumulator with the value 2h (0010b) and the carry flag set to logic one.
s3p7588x instructio n set 5- 81 sbc ? subtract with carry sbc dst,src operation: operand operation summary bytes cycles a,@hl subtract indirect data memory from a with carry 1 1 ea,rr subtract register pair (rr) from ea with carry 2 2 rrb,ea subtract ea from register pair ( rrb) with carry 2 2 description: sbc subtracts the source and carry flag value from the destination operand, leaving the result in the destination. sbc sets the carry flag if a borrow is needed for the most significant bit; otherwise it clears the carry flag. the contents of the source are unaffected. if the carry flag was set before the sbc instruction was executed, a borrow was needed for the previous step in multiple precision subtraction. in this case, the carry bit is subtracted from the destination along with the source operand. operand binary code operation notation a,@hl 0 0 1 1 1 1 0 0 c,a ? a ? (hl) ? c ea,rr 1 1 0 1 1 1 0 0 c, ea ? ea ?rr ? c 1 1 0 0 1 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 c,rrb ? rrb ? ea ? c 1 1 0 0 0 r2 r1 0 examples: 1. the extended accumulator contains the value 0c3h, register pair hl the value 0aah, and the carry flag is set to "1": scf ; c ? "1" sbc ea,hl ; ea ? 0c3h ? 0aah ? 1h, c ? "0" jps xxx ; jump to xxx; no skip after sbc 2. if the extended accumulator contains the value 0c3h, register pair hl the value 0aah, and the carry flag is cleared to "0": rcf ; c ? "0" sbc ea,hl ; ea ? 0c3h ? 0aah ? 0h = 19h, c ? "0" jps xx x ; jump to xxx; no skip after sbc
instruction set s3p 7588x 5- 82 sbc ? subtract with carry sbc (continued) examples: 3. if sbc a,@hl is followed by an ads a,#im, the sbc skips on 'no borrow' to the instruction immediately after the ads. an 'ads a,#im' instruction immediately after the 'sbc a,@hl' instruction does not skip even if an overflow occurs. this function is useful for decimal adjustment operations. a. 8 ? 6 decimal addition (the contents of the address specified by the hl register is 6h): rcf ; c ? "0" ld a,#8h ; a ? 8h sbc a,@hl ; a ? 8h ? 6h ? c(0) = 2h, c ? "0" ads a,#0ah ; skip this instruction because no borrow after sbc result jps xxx b. 3 ? 4 decimal addition (the contents of the address specified by the hl register is 4h): rcf ; c ? "0" ld a,#3h ; a ? 3h sbc a,@hl ; a ? 3h ? 4h ? c(0) = 0fh, c ? "1" ads a,#0ah ; no skip. a ? 0fh + 0ah = 9h ; (the skip function of 'ads a,#im' is inhibited after a ; 'sbc a,@hl' instruction even if an overflow occurs.) jps xxx
s3p7588x instructio n set 5- 83 sbs ? subtract sbs dst,src operation: operand operation summary bytes cycles a,@hl subtract indirect data memory from a; skip on borrow 1 1 + s ea,rr subtract register pair (rr) from ea; skip on borrow 2 2 + s rrb,ea subtract ea from register pair ( rrb); skip on borrow 2 2 + s description: the source operand is subtracted from the destination operand and the result is stored in the destination. the contents of the source are unaffected. a skip is executed if a borrow occurs. the value of the carry flag is not affected. operand binary code operation notation a,@hl 0 0 1 1 1 1 0 1 a ? a ? (hl); skip on borrow ea,rr 1 1 0 1 1 1 0 0 ea ? ea ? rr; skip on borrow 1 0 1 1 1 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 rrb ? rrb ? ea; skip on borrow 1 0 1 1 0 r2 r1 0 examples: 1. the accumulator contains the value 0c3h, register pair hl contains the value 0c7h, and the carry flag is cleared to logic zero: rcf ; c ? "0" sbs ea,hl ; ea ? 0c3h ? 0c7h, c ? "0" ; sbs instruction skips on borrow, ; but carry flag value is not affected jps xxx ; skip because a borrow occurred jps yyy ; jump to yyy is executed 2. the accumulator contains the value 0afh, register pair hl contains the value 0aah, and the carry flag is set to logic one: scf ; c ? "1" sbs ea,hl ; ea ? 0afh ? 0aah, c ? "1" jps xxx ; jump to xxx ; jps was not skipped since no "borrow" occurred after sbs
instruction set s3p 7588x 5- 84 scf ? set carry flag scf operation: operand operation summary bytes cycles ? set carry flag to logic one 1 1 description: the scf instruction sets the carry flag to logic one, regardless of its previous value. operand binary code operation notation ? 1 1 1 0 0 1 1 1 c ? 1 example: if the carry flag is cleared to logic zero, the instruction scf sets the carry flag to logic one.
s3p7588x instructio n set 5- 85 smb ? select memory bank smb n operation: operand operation summary bytes cycles n select memory bank 2 2 description: the smb instruction sets the upper four bits of a 12-bit data memory address to select a specific memory bank. the constants 0, 1, and 15 are usually used as the smb operand to select the corresponding memory bank. all references to data memory addresses fall within the following address ranges: please note that since data memory spaces differ for various devices in the sam4 product family, the 'n' value of the smb instruction will also vary . addresses register areas bank smb 000h?01fh working registers 0 0 020h?0ffh stack and general-purpose registers 100h?1dfh general-purpose registers 1 1 1e0h?1ffh display registers f80h?fffh i/o-mapped hardware registers 15 15 the enable memory bank (emb) flag must always be set to "1" in order for the smb instruction to execute successfully for memory banks 0, 1, and 15. format binary code operation notation n 1 1 0 1 1 1 0 1 smb ? n (n = 0, 1, 15) 0 1 0 0 d3 d2 d1 d0 example: if the emb flag is set, the instruction smb 0 selects the data memory address range for bank 0 (000h?0ffh) as the working memory bank.
instruction set s3p 7588x 5- 86 srb ? select register bank srb n operation: operand operation summary bytes cycles n select register bank 2 2 description: the srb instruction selects one of four register banks in the working register memory area. the constant value used with srb is 0, 1, 2, or 3. the following table shows the effect of srb s ettings: erb setting srb settings selected register bank 3 2 1 0 0 0 0 x x always set to bank 0 0 0 bank 0 1 0 0 0 1 bank 1 1 0 bank 2 1 1 bank 3 note: 'x' = not applicable. the enable register bank flag (erb) must always be set for the srb instruction to execute successfully for register banks 0, 1, 2, and 3. in addition, if the erb value is logic zero, register bank 0 is always selected, regardless of the srb value. operand binary code operation notation n 1 1 0 1 1 1 0 1 srb ? n (n = 0, 1, 2, 3) 0 1 0 1 0 0 d1 d0 example: if the erb flag is set, the instruction srb 3 selects register bank 3 (018h?01fh) as the working memory register bank.
s3p7588x instructio n set 5- 87 sret ? return from subroutine and skip sret operation: operand operation summary bytes cycles ? return from subroutine and skip 1 3 + s description: sret is normally used to return to the previously executing procedure at the end of a subroutine that was initiated by a call o r calls instruction. sret skips the resulting address, which is generally the instruction immediately after the point at which the subroutine was called. then, program execution continues from the resulting address and the contents of the location addressed by the stack pointer are popped into the program counter. operand binary code operation notation ? 1 1 1 0 0 1 0 1 pc12?8 ? (sp + 1) (sp) pc7?0 ? (sp + 3) (sp + 2) emb,erb ? (sp + 5) (sp + 4) sp ? sp + 6 example: if the stack pointer contains the value 0fah and ram locations 0fah, 0fbh, 0fch, and 0fdh contain the values 1h, 0h, 5h, and 2h, respectively, the instruction sret leaves the stack pointer with the value 00h and the program returns to continue execution at location 0125h. during a return from subroutine, data is popped from the stack to the pc as follows: sp ? pc11 ? pc8 sp + 1 0 0 0 pc12 sp + 2 pc3 ? pc0 sp + 3 pc7 ? pc4 sp + 4 0 0 emb erb sp + 5 0 0 0 0 sp + 6
instruction set s3p 7588x 5- 88 stop ? stop operation stop operation: operand operation summary bytes cycles ? engage cpu stop mode 2 2 description: the stop instruction stops the system clock by setting bit 3 of the power control register (pcon) to logic one. wh]en stop executes, all system operations are halted with the exception of some peripheral hardware with special power-down mode operating conditions . in application programs, a stop instruction should be immediately followed by at least three nop instructions. this ensures an adequate time interval for the clock to stabilize before the next instruction is executed. operand binary code operation notation ? 1 1 1 1 1 1 1 1 pcon.3 ? 1 1 0 1 1 0 0 1 1 example: given that bit 3 of the pcon register is cleared to logic zero, and all systems are operational, the instruction sequence stop nop nop nop sets bit 3 of the pcon register to logic one, stopping all controller operations (with the exception of some peripheral hardware). the three nop instructions provide the necessary timing delay for clock stabilization before the next instruction in the program sequence is executed.
s3p7588x instructio n set 5- 89 vent ? load emb, erb, and vector address ventn dst operation: operand operation summary bytes cycles emb (0,1) erb (0,1) adr load enable memory bank flag (emb) and the enable register bank flag (erb) and program counter to vector address, then branch to the corresponding location. 2 2 description: the vent instruction loads the contents of the enable memory bank flag (emb) and enable register bank flag (erb) into the respective vector addresses. it then points the interrupt service routine to the corresponding branching locations. the program counter is loaded automatically with the respective vector addresses which indicate the starting address of the respective vector interrupt service routines. the emb and erb flags should be modified using vent before the vector interrupts are acknowledged. then, when an interrupt is generated, the emb and erb values of the previous routine are automatically pushed onto the stack and then popped back when the routine is completed. after the return from interrupt (iret) you do not need to set the emb and erb values again. instead, use bitr and bits to clear these values in your program routine. the starting addresses for vector interrupts and reset operations are pointed to by the ventn instruction. these addresses must be stored in rom locations 0000h?3fffh. generally, the ventn instructions are coded starting at location 0000h. the format for vent instructions is as follows: ventn d1,d2,addr emb ? d1 ("0" or "1") erb ? d2 ("0" or "1") pc ? addr (address to branch n = device-specific module address code (n = 0?n) operand binary code operation notation emb (0,1) erb (0,1) adr e m b e r b 0 a12 a11 a10 a9 a8 rom (2 x n) 7?6 ? emb, erb rom (2 x n) 5?4 ? 0, pc12 rom (2 x n) 3?0 ? pc12?8 rom (2 x n + 1) 7?0 ? pc7?0 (n = 0, 1, 2, 3, 4, 5, 6, 7) a7 a6 a5 a4 a3 a2 a1 a0
instruction set s3p 7588x 5- 90 vent ? load emb, erb, and vector address ventn (continued) example: the instruction sequence org 0000h vent0 1,0,reset vent1 0,1,intb vent2 0,1,int0 vent3 0,1,int1 nop nop vent5 0,1,intt0 vent6 0,1,intt1 causes the program sequence to branch to the reset routine labeled 'reset,' setting emb to "1" and erb to "0" when reset is activated. when a basic timer interrupt is generated, vent1 causes the program to branch to the basic timer's interrupt service routine, intb, and to set the emb value to "0" and the erb value to "1". vent2 then branches to int0, vent3 to int1, and so on, setting the appropriate emb and erb values.
s3p7588x instructio n set 5- 91 xch ? exchange a or ea with nibble or byte xch dst,src operation: operand operation summary bytes cycles a,da exchange a and data memory contents 2 2 a,ra exchange a and register ( ra) contents 1 1 a,@rra exchange a and indirect data memory 1 1 ea,da exchange ea and direct data memory con tents 2 2 ea,rrb exchange ea and register pair ( rrb) contents 2 2 ea,@hl exchange ea and indirect data memory contents 2 2 description: the instruction xch loads the accumulator with the contents of the indicated destination variable and writes the original contents of the accumulator to the source. operand binary code operation notation a,da 0 1 1 1 1 0 0 1 a ? da a7 a6 a5 a4 a3 a2 a1 a0 a,ra 0 1 1 0 1 r2 r1 r0 a ? ra a,@rra 0 1 1 1 1 i2 i1 i0 a ? ( rra) ea,da 1 1 0 0 1 1 1 1 a ? da,e ? da + 1 a7 a6 a5 a4 a3 a2 a1 a0 ea,rrb 1 1 0 1 1 1 0 0 ea ? rrb 1 1 1 0 0 r2 r1 0 ea,@hl 1 1 0 1 1 1 0 0 a ? (hl), e ? (hl + 1) 0 0 0 0 0 0 0 1 example: double register hl contains the address 20h. the accumulator contains the value 3fh (00111111b) and internal ram location 20h the value 75h (01110101b). the instruction xch ea,@hl leaves ram location 20h with the value 3fh (00111111b) and the extended accumulator with the value 75h (01110101b).
instruction set s3p 7588x 5- 92 xchd ? exchange and decrement xchd dst,src operation: operand operation summary bytes cycles a,@hl exchange a and data memory contents; decrement contents of register l and skip on borrow 1 2 + s description: the instruction xchd exchanges the contents of the accumulator with the ram location addressed by register pair hl and then decrements the contents of register l. if the content of register l is 0fh, the next instruction is skipped. the value of the carry flag is not affected. operand binary code operation notation a,@hl 0 1 1 1 1 0 1 1 a ? (hl), then l ? l?1; skip if l = 0fh example: register pair hl contains the address 20h and internal ram location 20h contains the value 0fh: ld hl,#20h ld a,#0h xchd a,@hl ; a ? 0fh and l ? l ? 1, (hl) ? "0" jps xxx ; skipped since a borrow occurred jps yyy ; h ? 2h, l ? 0fh yyy xchd a,@hl ; (2fh) ? 0fh, a ? (2fh), l ? l ? 1 = 0eh ? ? ? the ' jps yyy' instruction is executed since a skip occurs after the xchd instruction.
s3p7588x instructio n set 5- 93 xchi ? exchange and increment xchi dst,src operation: operand operation summary bytes cycles a,@hl exchange a and data memory contents; increment contents of register l and skip on overflow 1 2 + s description: the instruction xchi exchanges the contents of the accumulator with the ram location addressed by register pair hl and then increments the contents of register l. if the content of register l is 0h, a skip is executed. the value of the carry flag is not affected. operand binary code operation notation a,@hl 0 1 1 1 1 0 1 0 a ? (hl), then l ? l+1; skip if l = 0h example: register pair hl contains the address 2fh and internal ram location 2fh contains 0fh: ld hl,#2fh ld a,#0h xchi a,@hl ; a ? 0fh and l ? l + 1 = 0, (hl) ? "0" jps xxx ; skipped since an overflow occurred jps yyy ; h ? 2h, l ? 0h yyy xchi a,@hl ; (20h) ? 0fh, a ? (20h), l ? l + 1 = 1h ? ? ? the ' jps yyy' instruction is executed since a skip occurs after the xchi instruction.
instruction set s3p 7588x 5- 94 xor ? logical exclusive or xor dst,src operation: operand operation summary bytes cycles a,#im exclusive-or immediate data to a 2 2 a,@hl exclusive-or indirect data memory to a 1 1 ea,rr exclusive-or register pair (rr) to ea 2 2 rrb,ea exclusive-or register pair ( rrb) to ea 2 2 description: xor performs a bitwise logical xor operation between the source and destination variables and stores the re sult in the destination. the source contents are unaffected. operand binary code operation notation a,#im 1 1 0 1 1 1 0 1 a ? a xor im 0 0 1 1 d3 d2 d1 d0 a,@hl 0 0 1 1 1 0 1 1 a ? a xor (hl) ea,rr 1 1 0 1 1 1 0 0 ea ? ea xor (rr) 0 0 1 1 0 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 rrb ? rrb xor ea 0 0 1 1 0 r2 r1 0 example: if the extended accumulator contains 0c3h (11000011b) and register pair hl contains 55h (01010101b), the instruction xor ea,hl leaves the value 96h (10010110b) in the extended accumulator.
s3p7588x oscillator circuits 6- 1 6 oscillator circuits overview the s3p7588x microcontrollers have one oscillator circuit, the system clock circuit, ( fx). the cpu and peripheral hardware operates on the system clock frequency supplied through this circuit. specifically, a clock pulse is required by the following peripheral modules: ? basic timer ? timer/counters 0 ? watch timer ? clock output circuit clock control registers the power control register, pcon, is used to select normal cpu operating mode or one of two power-down modes ? stop or idle. bits 3 and 2 of the pcon register can be manipulated by a stop or idle instruction to engage stop or idle power-down mode. the system clock frequencies can be divided by 4, 8, or 64. by manipulating pcon bits 1 and 0, you select one of the following frequencies as the selected system clock. fx 4 , fx 8 , fx 64
oscillator circuits s3p7588x 6- 2 main system oscillator circuit x out x in 1 - 1/4096 frequency dividing circuit 1/2 1/16 selector dtmf generator watch timer basic timer timer/counter 0.1 clock output circuit oscillator control circuit 1/4 cpu clock pcon.0 pcon.1 pcon.2 pcon.3 idle stop pcon.3, .2 clear wait release signal internal reset signal power-down release signal cpu stop signal (idle mode) fx oscillator stop setting the cpu clock figure 6-1. clock circuit diagram
s3p7588x oscillator circuits 6- 3 system oscillator circuits x in x out figure 6-2. crystal/ceramic oscillator x in x out figure 6-3. external oscillator
oscillator circuits s3p7588x 6- 4 power control register (pcon) the power control register, pcon, is a 4-bit register that is used to select the cpu clock frequency and to control cpu operating and power-down modes. pcon can be addressed directly by 4-bit write instructions or indirectly by the instructions idle and stop. fb3h pcon.3 pcon.2 pcon.1 pcon.0 pcon bits 3 and 2 are addressed by the stop and idle instructions, respectively, to engage the idle and stop power-down modes. idle and stop modes can be initiated by these instruction despite the current value of the enable memory bank flag (emb). by manipulating bits 1 and 0 of the pcon register, the system clock frequency can be divided by 4, 8, or 64. reset sets pcon register values to logic zero: pcon.1 and pcon.0 divide the fx frequency by 64, and pcon.3 and pcon.2 enable normal cpu operating mode. table 6-1. power control register (pcon) organization pcon bit settings resulting cpu operating mode pcon.3 pcon.2 0 0 normal cpu operating mode 0 1 idle power-down mode 1 0 stop power-down mode pcon bit settings resulting cpu clock frequency pcon.1 pcon.0 0 0 fx/64 1 0 fx/8 1 1 fx/4 f f programmingng tip ? setting the cpu clock to set the cpu clock to 1.05mhz at 4.19mhz: bits emb smb 15 ld a,#3h ld pcon,a
s3p7588x oscillator circuits 6- 5 instruction cycle times the unit of time that equals one machine cycle varies depending on how the oscillator clock signal is divided (by 4, 8, or 64) by the system clock. table 6-2 shows corresponding cycle times in microseconds. table 6-2. instruction cycle times for cpu clock rates selected cpu clock resulting frequency oscillation source cycle time ( sec) fx/64 65.5khz fx = 4.19mhz 15.3 fx/8 524.0khz 1.91 fx/4 1.05mhz 0.95 clock output mode register (clmod) the clock output mode register, clmod, is a 4-bit register that is used to enable or disable clock output to the clo pin and to select the cpu clock source and frequency. clmod is addressable by 4-bit write instruction only. fd0h clmod.3 ?0? clmod.1 clmod.0 reset clears clmod to logic zero, which automatically selects the cpu clock as the clock source (without initiating clock oscillation), and disable clock output. clomd.3 is the enable/disable clock output control bit; clomd.1 and clomd.0 are used to select one of four possible clock sources and frequencies: normal cpu clock, fx/8, fx/16, or fx/64. table 6-3. clock output mode register (clmod) organization clmod bit setting resulting clock output clmod.1 clmod.0 clock source frequency 0 0 cpu clock (fx/4, fx/8, fx/64) 1.05mhz,524khz, 65.5khz 0 1 fx/8 524khz 1 0 fx/16 262khz 1 1 fx/64 65.5khz clmod.3 result of clmod.3 setting 0 clock output is disable 1 clock output is enable note: frequencies assume that fx = 4.19mhz.
oscillator circuits s3p7588x 6- 6 clock output circuit the clock output circuit, used to output clock pulses to the clo pin, has the following components: ? 4-bit clock output mode register (clmod) ? clock selector ? output latch ? port mode flag ? clo output pin (p2.2) clmod.3 clmod.2 clmod.1 clmod.0 4 clock selector p9.2 output latch pm9 clo clocks (fx/8, fx/16, fx/64, cpu clock) figure 6-4. clo output pin circuit diagram clock output procedure the procedure for outputting clock pulses to the clo pin may be summarized as follows: ? disable clock output by clearing clmod.3 to logic zero. ? set the clock output frequency (clmo d.1, clmod.0). ? load a ?0? to the output latch of the clo pin (p9.2). ? set the p9.2 mode flag (pm 9) to output mode. ? enable clock output by setting clmod.3 to logic one. f f programming tip ? cpu clock output to the clo pin to output the cpu clock to the clo pin bits emb smb 15 ld ea,#040h ld pmg4,ea ; p 9.2 ? output mode bitr p9.2 ; clear p9.2 output latch ld a,#8h ld clmod,a
s3p7588x caller id 7- 1 7 caller id overview the s3p7588x has a caller id receiver unit in which it has the following features. ? 1200 baud fsk (frequency shift keying) demodulator with sensitivity ?38dbm (600 w ) confirms to bell 202 and ccitt v.23 standards ? cas receiver with receive sensitivity of ?32dbm (in 600 w ) ? stutter dial tone (sdt) detector with sensitivity of -36dbm ? ring or line reversal detector ? on-hook and off-hook applications according to bellcore tr-nwt-000030 and sr-tsv-002476 specifications ? compatible with etsi standards ets 300 659-1 and ets 3000 659-2
caller id s3p7588x 7- 2 application board configuration for developing caller id application when the test board is designed, you must acknowledge the s3p7588x?s operating modes. there are three modes for s3p7588x. 1. normal operating mode this mode is a normal operating mode as it is. in this mode internal mcu and caller id are cooperate with 4 signals. these signals are viewed as ports in programmers view. that is, programmers can control the caller id as if it is connected to the external i/o ports. these i/o ports and it?s functions are as follows. table 7-1. interconnections between internal mcu and caller id programmers view caller id signal function p1.0 int caller id interrupt request p2.1 sck sck signal for i 2 c interfacing with caller id p2.2 sdt sdt signal for i 2 c interfacing with caller id p3.1 (or p8.0) cid_resetb reset signal dedicated to caller id block because ks57c5308 doesn?t have p8 ports, p3.1 is used instead as default reset signal. but if you develop application with ks57c5208 smds, you can use p8.0 by setting p8.1 to logic-1 ahead. (note) note: the caller id receiver remains in reset state during this dedicated signal is not re leased. that is, the caller id receiver can be released from reset state only by toggling the dedicated signal. (high ? low ? high) 2. caller id mode in this mode, internal mcu is disabled and s3p7588x is operating as if it is a caller id chip. this mode is useful when you develop some application system with s3p7588x device. s3p7588x?s functions are compatible to ks57c5208/ks57c5308 device so you can utilize the smds system of ks57c5208/ s57c5308 without modification with s3p7588x configured as t his mode. when caller id mode is enabled, 7 pins are assigned as follows for caller id interfacing.
s3p7588x caller id 7- 3 table 7-2. pin assignment in caller id mode pin name caller id signal function p9.0 int caller id interrupt request p9.1 sck sck signal for i 2 c interfacing with caller id p9.2 sdt sdt signal for i 2 c interfacing with caller id p1.1 cid_resetb reset signal dedicated to caller id block p1.2, p3.0, p3.1 ? must be tied to ground. note: other ports must be floated from the development board. that is smds board must feed these ports to the development board. (see figure 7-1) so, when you develop some application system, you first develop a s/w for your system with this mode, then download it to s3p7588x?s otp rom and test if it runs correctly in normal operating mode. 3. otp programming mode in this mode, you can download your own program to internal eprom. it is useful in that it can diminish the risk of mask-rom version, and is helpful for s/w development. refer to chapter 15 for detailed o tp programming method. these three modes can be selected by configuring external pins. table 7-3 represents this configurations. table 7-3. pin configurations for selecting operation modes test resetb operation mode 0 1 normal operation mode 1 0 caller id mode v pp (12.5v) 0 otp programming mode figure 7-1 represents overall interconnection between the development board and smds of ks57c5208/ ks57c5308.
caller id s3p7588x 7- 4 s3p7588x (caller id mode) smds tb5208b / tb5308b adapter p8.0 / p3.1 p1.0 p2.1 p2.2 p1.1 p9.0 p9.1 p9.2 other pins mean p1.1~p1.3, p2.0, p2.3, p3, p4, p5, p6, p7, p9. other pins (note 1) xin xin caller id application circuit ins inp inn out vref lrin dtmf floated pins (note 2) test resetb p3.0 p3.1 p1.2 r (note 3) notes : 1. s3p7588x pins except that used in caller id mode are to be floated from the application board. 2. pullup resistor is needed because p9.0 and p9.2 are changed to open-drain type in caller id mode. 3. because ks57c5308 doesn't have p8 port, p3.1 is to be used as the caller id reset signal instead of p8.0 when you develop with ks57c5308 smds. for s/w compatibility between ks57c5308 and ks57c5208 smds, internal default port of caller id reset signal is p3.1, so if you use ks57c5208 smds and want to use p3.1 for other purpose, set p8.1 to logic high ahead then p8.0 is used as caller id reset signal. 4. figure 7-1. application diagram for s3p7588x development system with ks57c5208 smds
s3p7588x caller id 7- 5 analog application diagram all analog parts in s3p7588x are related to interfacing between caller id and telephone line. figure 7-2 and table 7-4 represents the recommended diagram and it?s component values for typical application. note that t he components specified are for a typical application. for conformance to standards in certain applications, other component values and/or ratings may be necessary. tip/a r1b d1 d2 d3 d4 r2a r2b r3 r4 r5 line c6 c5 3.579545mhz r8 c2 r9 d6 d5 p1 r11 r10 c3 r1a in out ring/b c1a c1b r6 r7 c4 s3p7588x lrin xin xout vref ins inp dtmf test inn out r12 c8 figure 7-2. recommended diagram for typical application
caller id s3p7588x 7- 6 table 7-4. recommended external component values for typical application differential input stage single ended input stage c1a, c1b 2.2nf (1kv) c4 100nf r1a, r1b 390k w (0.5w) r6 (note) 100k w r2a, r2b 47k w r7 (note) 100k w r3 68k w crystal oscillator r4 220k w c5,c6 20pf r5 100k w x1 3.579545mhz 0.1% d1, d2, d3, d4 in4007 o1 lm358 ring or line reversal detector c2 0.22uf (250v) r10,r11 20k w c3 10nf d5 24v r8 36k w d6 1n4148 r9 3.9k w p1 pc817/ltv817 dc input stage tone generator c8 10nf r12 2.0k w note: values for r6 and r7 are based on a hybrid that has a loss free path from line to out
s3p7588x caller id 7- 7 functional descriptions of caller id block functional block diagram adc bandpass filter fsk receiver bandpass filter p9.0 (int) p9.1 (sck) p9.2 (sdt) lrin out inn inp ins vref cas detector stutter dial tone detector line reversal / ring detector bias voltage vdda vssa mode control & serial interface figure 7-3. block diagram of cid module
caller id s3p7588x 7- 8 analog input and preprocessor the preprocessor for the fsk receiver and the cas , the sdt detectors , comprises two input signal buffers , an 14bit analog-to-digital converter (adc) and digital bandpass filters. bandpass filters are used to attenuate out band noise and interfering signals , which might otherwise reach the fsk receiver and cas , sdt detectors. the cas and sdt detectors share a single digital filter while the fsk receiver has its own separate filter. the cid block can be forced into a power-down state by switching off the 3.579545mhz system clock and adc and op-amps. differential input buffer the differential input buffer is used to convert the balanced telephone line signal to the input signal of adc in the cid block. s3p7588x tip/a ring/b r1a c1a to 14-bit adc r3 r1b c1b r4 r5 inp inn out vref figure 7-4. differential input buffer of s3p7588x design equations for this buffer are the differential voltage gain = r5/r1b. r1a = r1b c1a = c1b r3 = r4 * r5 / (r4 + r5) the target differential voltage gain should be adjusted to obtain the expected signal level at the ?out? pin. single ended input buffer the single ended input buffer may also be used with the telephone line signal connected to the hybrid as shown in figure 7-5. the voltage gain is r7 / ( r6 + r7 ) the target voltage gain should be adjusted to obtain the expected signal level at the ins input. the bfs (buffer selection) bit in the function register chooses between the output of the single-ended input buffer and the output of the differential input buffer, sending the selected output to the adc. the differential input buffer is selected when bfs is ?0? and the single ended input buffer is selected when bfs is ?1?. the default value of bfs is ?0?
s3p7588x caller id 7- 9 s3p7588x a r6 c4 to 14-bit adc r7 ins vref connected to hybrid figure 7-5. single ended buffer of s3p7588x cas tone detection the cas detection block is capable of detecting the cas signals during speech with high talk-down and talk-off performance without the use of a hybrid , and 100% bellcore compliant performance with the use of a hybrid. if the cas detection is enabled the caller id block will generate an interrupt (interrupt register , bit 1 is set) when a correct dual tone (2130 and 2750hz) is detected. cas detection is enabled when the casenable bit in the function register is set and the fsk and sdt enable bits in the function register are cleared. the parameters of the cas detector are shown in table 7-5. table 7-5. cas detector parameters parameter value low tone frequency 2130hz 0.5% high tone frequency 2750hz 0.5% accepted signal level -5.2dbm to ?32dbm twist -6db to +6db when a valid cas signal is detected , the casdetect status bit of the status register and the casint bit of the interrupt register are set and an interrupt is generated. when the signal level is below the accepted signal level the status bit of the status register is cleared and the casint interrupt bit is set , generating another interrupt. the casint interrupt bit is reset when the interrupt register is read (see figure 7-6). line signal casdetect int cas signal interrupt register is read figure 7-6. casdetect , casint and int related to the cas tone in order to accurately detect the end of a cas tone , it is recommended to mute the near end speech immediately after the cas tone has been detected.
caller id s3p7588x 7- 10 fsk reception fsk data reception sequence the on-chip fsk receiver satisfies all target specifications of bellcore. the fsk receiver function can be enabled by setting the fskenable bit (function register , bit2) and clearing the casenable (function register , bit1) and the sdtenable (function register , bit5) bits. when the fsk receiver is enabled , the cid block continuously checks for a signal in the fsk band (~1200 - ~2200hz) above the minimum signal level threshold. an fsk data word consists of one start bit (space) followed by eight data bits and one stop bit (mark). after the fsk receiver has detected a start bit it starts receiving the data bits (lsb first). after the 8 th data bit the fskint interrupt bit (interrupt register, bit2) is set and an interrupt is generated. the fskint interrupt bit is cleared when the interrupt register is read. the interrupt register and the fskdt register should be read every time an interrupt occurs. fsk data fskint int d d1 d2 d3 d4 d5 d6 d0 d7 interrupt register is read figure 7-7. sequence to receive an fsk data byte table 7-6. fsk receiver parameters parameter bellcore ccitt / v23 mark frequency (logic 1) 1200hz 1% 1300hz 1.5% space frequency (logic 0) 2200hz 1% 2100hz 1.5% maximum allowed signal level 0dbm -8dbv minimum signal level threshold < -38dbm < -40dbv twist -10db to +10db -6db to +6db accepted s/n (0hz ? 200hz) < -20db < -20db accepted s/n (200hz ? 3200hz) < 6db < 6db accepted s/n (3200hz ? 15000hz) < -20db < -20db transmission rate 1200 bits per second 1% 1200 bits per second 1%
s3p7588x caller id 7- 11 begin of mark (bom) detection bomdc bit of mode register (mode register, bit 6) is utilized for detecting begin of mark or channel seizure. if bomdc is set to '0', the bomdetect signal (intr register, bit 6) will be set after the begin of mark has been detected, and if bomdc is '1', bomdetect will be set after the channel seizure detected. when bomdc is '1' and bomdetect is set, the interrupts occur due to channel seizure and the value of fskdt will be 55h as shown in figure 7-8. if bomdc is '0', interrupt will therefore not be generated during the channel seizure and during the block of marks as shown in figure 7-9. the fsk interrupts of data bytes will be generated after a mark period of at least 16 sequential 1?s has been detected. behavior of bomdetect (stat register, bit 4) is shown in figure 7-8 and 7-9. this bit will be cleared when the fsk receiver is disabled or a signal drop out occurs for more than 18.3ms. in the latter case the fsk receiver will behave as if it has just been disabled. noise noise fsk transmission line signal mark data lnterrupts due to channel seizure fskdt = 55h channel seizure(optional) fsk enabie bomdetect int when bomdc = 1 figure 7-8. interrupt behavior of the fsk receiver with bomdc = 1 noise noise fsk transmission line signal mark data channel seizure(optional) fsk enabie bomdetect int when bomdc = 0 figure 7-9. interrupt behavior of the fsk receiver with bomdc = 0 during fsk data reception , no new interrupts will occur after a signal dropout when bomdc = '0'. if it is necessary to receive as much data as possible (even with a part missing) then the bomdc can be set to '1' when reception of data starts.
caller id s3p7588x 7- 12 stutter dial tone (sdt) detector this block is enabled when the s3p7588x is set to sdt enable mode (function register, bit5) and all the other functions in the function register are disabled. the detector measures the total signal level for every 31.5ms. when the total signal level is above -36dbm in the 350hz to 440hz dial tone band, the sdtdetect bit in the status register is set. when the total signal level is below ?36dbm the sdtdetect bit is cleared (see table 7-7). each time sdtdetect changes the sdtint bit is set and an interrupt is generated. the sdtint bit is cleared when the interrupt register is read. this behavior is shown in figure 7-10. line signal ptedetect int sdt signal sdt signal lnterrupt register is read lnterrupt register is read lnterrupt register is read lnterrupt register is read figure 7-10. sdt detector operation table 7-7. stutter dial tone parameters parameters values frequencies 330hz to 440hz signal amplitude power -10dbm to -36dbm duration 80 to 160ms on/off, with a duty cycle from 40% to 60% ring or line reversal detector for ring or line reversal detection, some external components are needed to generate a pulse each time a ring or line reversal occurs, as shown in figure 7-11. interrupt generation of the ring or line reversal detector is controlled by the lrenable bit in the function register. when lrenable is set to ?1?, the lrint bit of the interrupt register will be set and interrupts will be generated at every transition of the lrstatus bit. when lrenable is ?0?, interrupts will not be generated. the lrstatus bit (reset value is high) in the status register is cleared to ?0? when lrin is high. if no positive edges of lrin are detected in tguard time the lrstatus bit is set to ?1?. the lrint bit is cleared when the interrupt register is read. if an lrint interrupt has been generated in power-down mode, it is recommended to disable power-down mode to be able to count the guard time counter using the main clock (xin). the guard time counter is reset at the positive edge of lrin. the guard time ( tguard) can be programmed by writing the gtime register as follows. tguard = 183us * ( gtime[6:0] * 4 + 3 ) (ex. tguard = 44,469ms = 0.153ms * (0111100b * 4 + 3 ) )
s3p7588x caller id 7- 13 lrin s3p7588x tip/a ring/b r8 c2 to ring/line reversal detector r9 d6 d5 p1 r11 r10 c3 figure 7-11. external component to generate lrin the following figures are shown for the behavior of line reversal and ring detection respectively. line signal lrin lrstatus lrint int pwd = 0 t guard pwd = 1 lrenable = 1 interrupt register is read figure 7-12. behavior of signals on a line reversal
caller id s3p7588x 7- 14 interrupt register is read line signal lrin lrstatus lrint int t guard interrupt register is read figure 7-13. behavior of signals during ring dtmf generator the dtmf generator is able to generate 16 standard dual tones (see table 7-8). these tones can be programmed by writing the dtmf register via the serial interface or directly writing dtmr(fd2h), dtgr(fd4h) register with ? ld? instruction. that is, there are two method to control dtmf generator, one is to use caller id register and the other is to use memory mapped register of dtmf generator. there are only caller id registers described in this chapter. please refer to chapter 13 to know about the memory mapped registers. it is recommended to use caller id?s register because you?d better to use s3p7588x?s dtmf output rather than ks57c5208/ks57c5308 smds?s dtmf output. when you develop your own application system by setting s3p7588x as caller id mode, all registers except that of caller id are unable to be used, so if you use memory mapped register of dtmf generator, smds?s dtmf generator is activated instead of s3p7588x?s one. the dtmf generator is enabled when the dtmfenable bit (function register, bit3) is set to ?1?. when the dtmft.7 (on/off) bit is programmed to '0', no tone will be generated; when it is programmed to '1', the tone specified in dtmft.3 to dtmft.0 will be generated. the code for each dual tone is shown in table 7-8. the dtmfg register can control the output gain of dtmf signal. the default power of the dtmf signal is ?7.5 dbm for high tone and ?9.5dbm for low tone. the dtmfg register contains the gain factor that is multiplied to the default signal power to obtain the dtmf signal power. the gain factor is an unsigned number. the most significant bit (m) of the dtmfg register is the mantissa and the remaining bits (e6 to e0) denote the exponent. the output power of the dtmf signal can be obtained by the following equation. dtmf signal power = default signal power * dtmfg symbol 7 6 5 4 3 2 1 0 dtmfg m e6 e5 e4 e3 e2 e1 e0
s3p7588x caller id 7- 15 the dtmfg register can be programmed within the range from 0.0000001b (0.0078 in decimal) to 1.1000111b (1.5546 in decimal). for example, if dtmfg is set to 80h (1.0000000 in binary or 1.0 in decimal) the dtmf signal power will be the same as the default power. if the dtmfg register is 0.1100110h (0.7969 in decimal) the dtmf signal power will be 1.97db lower than the default power as follows. 20log(default power*0.7969 ? default power) = 20log 0.7969 = -1.97db the high tone power = -9.47db the low tone power = -11.47db when you want to use memory mapped register of dtmf generator (dtmr, dtgr), you should write zero to dtmft register and 80h to dtmfg register ahead. table 7-8. dtmf frequencies code table d3 d2 d1 d0 character low frequency high frequency 0 0 0 1 1 697.0hz 1209hz 0 0 1 0 2 697.0hz 1336hz 0 0 1 1 3 697.0hz 1477hz 0 1 0 0 4 770.0hz 1209hz 0 1 0 1 5 770.0hz 1336hz 0 1 1 0 6 770.0hz 1477hz 0 1 1 1 7 852.0hz 1209hz 1 0 0 0 8 852.0hz 1336hz 1 0 0 1 9 852.0hz 1477hz 1 0 1 0 0 941.0hz 1336hz 1 0 1 1 * 941.0hz 1209hz 1 1 0 0 # 941.0hz 1477hz 1 1 0 1 a 697.0hz 1633hz 1 1 1 0 b 770.0hz 1633hz 1 1 1 1 c 852.0hz 1633hz 0 0 0 0 d 941.0hz 1633hz serial interface the data interface between caller id and mcu block is a serial interface. this interface is processed through the internal p2.1 (sck) and p2.2 (sdt) signal. the sck is a transmission clock and the sdt transmits bi-directional data. the mcu always initiates a transmission and generates the transmission clock on the sck line.
caller id s3p7588x 7- 16 start and stop conditions the sdt and sck lines remain high when the bus is not busy. a high-to-low transition of the sdt line while the sck is high is defined as the start condition. a low-to-high transition of the sdt while the sck is high is defined as a stop condition. when a start condition occurs between a normal start condition and a stop condition, this is called a repeated start condition. sck sdt start condition stop condition figure 7-14. start and stop conditions bit transfer sck sdt data line stable; data valid data can be changed figure 7-15. bit transfer timing
s3p7588x caller id 7- 17 byte transfer and acknowledge the number of data bytes transferred between the start and the stop conditions from the transmitter to the receiver is unlimited. each byte of eight bits is followed by an acknowledge bit. the acknowledge bit is a high level signal put on the bus by the transmitter during which time the micro-controller generates an extra acknowledge-related clock pulse. the caller id block must generate an acknowledge bit after the reception of address field data or a register start address. also the micro-controller must generate an acknowledge bit after the reception of each byte that has been clocked out of the caller id block. the device that acknowledges must pull down the sdt line during the acknowledge clock period immediately after the 8 th sck pulse, so that the sdt line is stable low during the high period of the acknowledge-related sck pulse. the micro-controller must signal an end-of-data to the caller id block by not generating an acknowledge on the last byte that has been clocked out of the caller id block. in this event the caller id block must leave the sdt line high to enable the micro-controller to generate a stop condition. d7 d6 d5 d4 d3 d2 d1 d0 d7 ack sck from micro controller sdt by transmitter sdt by receiver figure 7-16. byte transmission and acknowledge address field before any data is transmitted on the sdt line, the caller id block, which should respond, is addressed first. the addressing is always carried out with the first byte (address field) transmitted after the start procedure. the interface address is reserved for the caller id block, 30h for write and 31h for read. when the address matches the address of the caller id block, the acknowledge is given; when it does not match, no acknowledge is given. the address field is built of two parts as follows ? interface address (a6 to a0) ? read/write control (r/ w ) table 7-9. bit specification of the address field a6 a5 a4 a3 a2 a1 a0 r/w 0 0 1 1 0 0 0 1/0
caller id s3p7588x 7- 18 register address the register address is the second byte transmitted by the micro-controller. this address is stored in the cid block and used for the following read and write actions. when multiple bytes are accessed, the first byte is written to the specified register address and the register address of the cid block is auto-incremented on each acknowledge. serial communication protocol the serial communication protocol is shown in figure 7-17 and figure 7-18. the micro-controller can initiate two kinds of sequence, the write sequence and the read sequence. both sequences are initiated with a start condition that is followed by the caller id block address with the read/write control bit cleared. the first byte after the caller id block address is interpreted as the address of a caller id block register. during the write sequence the register address of the caller id block is increased automatically on each acknowledge. the write sequence is ended with the stop condition from the micro-controller. address field stop a a a start register address data acknowledgement from cid part of s3p7588x acknowledgement from cid part of s3p7588x acknowledgement from cid part of 3p7588x auto increment register address r / w 0 figure 7-17. write sequence of the serial interface for the read sequence, after a register address of the caller id block, a repeated start condition is generated by the micro-controller which is followed by the caller id block address with the read/write control bit set. the data is read from the previously set register address. when the micro-controller responds with an acknowledge the address of the register is auto incremented and the caller id block will put the data from the next register on the sdt line. when the micro-controller stops giving an acknowledge the caller id block will stop transmitting data and the micro-controller will generate a stop condition. when the read sequence is initiated with a start condition that is followed by the caller id block address with the read/write control bit set, the data is read from the last set register address. (see figure 7-18)
s3p7588x caller id 7- 19 address field register address data auto increament register address a a a start stop 0 acknowledgement from cid part r/ w acknowledgement from cid part acknowledgement from mcu part start address field a 1 acknowledgement from cid part r/ w repeated start data 1 no acknowledgement from mcu part figure 7-18. (a) read sequence of the serial interface when new register start address is programmed address field data auto increament register address a a start stop 1 acknowledgement from cid part r/ w acknowledgement from mcu part data 1 no acknowledgement from mcu part figure 7-18. (b) read sequence of the serial interface when no register start address is programmed power-down mode the caller id block can be put in power-down mode by programming the pdw bit in the mode register to '1'. in this mode the input signal buffers, adc, the reference bias generator and the internal clock are switched off. however the ring/line reversal detection can be active by programming the lrenable bit in the function register to be set. the serial interface can always be accessed, even in power-down mode. in power-down mode, if ring or line reversal occurs when lrenable bit is ?1?, the lrint bit is set and an interrupt is generated. when the caller id block is put in power-down mode, all interrupt bits in the interrupt register cannot be set except for the lrint bit.
caller id s3p7588x 7- 20 interrupt the interrupt signal of caller id is active low. so it must be programmed that int0 interrupt is falling edge detection mode. the flag in the interrupt register of caller id indicates the interrupt cause. interrupt flags are set by hardware but must be reset by software. all flags of the interrupt register are reset when the register is read via the serial interface. the table 7-10 shows interrupt sources of the cid block. table 7-10. interrupt sources of the cid block source block generation ring / line reversal detector when lrstatus changes fsk receiver reception of a new fsk data byte cas detector when casdetect changes sdt detector when sdtdetect changes
s3p7588x caller id 7- 21 register maps of caller id block the registers that are available in the caller id block are shown in the following tables. table 7-11. register overview register name address function default value read / write mode 00h mode register 0000 0000 read / write func 01h function register 0000 0000 read / write dtmft 02h dtmf tone select register 0000 0000 read / write gtime 0ah guard time register 0000 0000 read / write intr 80h interrupt register 0000 0000 read only stat 81h status register 0000 0100 read only fskdt 82h fsk data register 0000 0000 read only dtmfg f0h dtmf output gain control register 0000 0000 read / write cont1 f1h special control register 1 0000 0000 read / write cont2 f5h special control register 2 0000 0000 read / write
caller id s3p7588x 7- 22 mode register (mode) address 00h; read / write. 7 6 5 4 3 2 1 0 pdw bomdc - - - - - - description of mode bits bit symbol description mode.7 pwd 1: puts the cid part of cid block in power-down mode 0: puts the cid part of cid block in active mode mode.6 bomdc 0: forbids fsk interrupts until bomdc is ?1? 1: allows fsk interrupts before bomdc is ?0? function register (func) address 01h; read / write. 7 6 5 4 3 2 1 0 bfs - sdtenable - dtmfenable fskenable casenable lrenable description of func bits bit symbol description func.7 bfs 1: selects the single-ended input buffer 0: selects the differential input buffer func.5 sdtenable 1: enables the sdt detector 0: disables the sdt detector func.3 dtmfenable 1: enables the dtmf generator 0: disables the dtmf generator func.2 fskenable 1: enables fsk receiver 0: disables fsk receiver func.1 casenable 1: enables cas detector 0: disables cas detector func.0 lrenable 1: enables lr interrupts 0: disables lr interrupts
s3p7588x caller id 7- 23 dtmf tone select register (dtmft) address 02h; read / write. 7 6 5 4 3 2 1 0 on-off - - - t3 t2 t1 t0 description of dtfmt bits bit symbol description dtmft.7 on-off 1: enables dtmf tone output 0: disables dtmf tone output dtmft.3 to dtmft.0 t3 to t0 dtmf code to be generated (see table 7) guard time register (gtime) address 0ah; read / write. 7 6 5 4 3 2 1 0 - g6 g5 g4 g3 g2 g1 g0 description of gtime bits bit symbol description gtime.6 to gtime.0 d6 to d0 guard time to indicate the end of a line reversal or ring interrupt register (intr) address 80h; read only. 7 6 5 4 3 2 1 0 - bomdetect sdtint - - fskint casint lrint description of intr bits bit symbol description intr.6 bomdetect 1: indicates that the begin of the mark period during fsk reception has been detected intr.5 sdtint 1: indicates that sdtdetect has been changed intr.2 fskint 1: indicates that a new fsk frame has been received intr.1 casint 1: indicates that casdetect has been detected intr.0 lrint 1: indicates that lrstatus has been changed
caller id s3p7588x 7- 24 status register (stat) address 81h; read only. 7 6 5 4 3 2 1 0 - - sdtdetect - - - casdetect lrstatus description of stat bits bit symbol description stat.5 sdtdetect 1: indicates that the sdt detector detects the signal that satisfies the specified frequency and energy level; 0: no more progress tone is detected stat.1 casdetect 1: indicates that a cas tone has been detected 0: no more cas tone is detected stat.0 lrstatus 1: lrint has not occurred until expiring gtime (reset value) 0: lrint has occurred before expiring gtime fsk data register (fskdt) address 82h; read only. 7 6 5 4 3 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 description of fskdt bits bit symbol description fskdt.7 to fskdt.0 d7 to d0 last received fsk data byte dtmf output gain control register (dtmfg) address 0h; read / write 7 6 5 4 3 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 description of dtmfg bits bit symbol description dtmfg.7 to dtmfg.0 d7 to d0 this byte multiplied to control the output gain of dtmf generator
s3p7588x caller id 7- 25 special control register (cont1) address f1h; read / write 7 6 5 4 3 2 1 0 - - 0 0 0 1 1 1 this register should be written with ?xx00 0111b?. special control register (cont2) address f5h; read / write 7 6 5 4 3 2 1 0 - - 0 0 0 0 0 0 this register should be written with ?xx00 0000b?.
caller id s3p7588x 7- 26 notes
s3p7588x interrups 8- 1 8 interrupts overview the s3p7588x interrupt control circuit has five functional components: ? interrupt enable flags ( iex) ? interrupt request flags ( irqx) ? interrupt mask enable register (ime) ? interrupt pr iority register (ipr) ? power-down release signal circuit three kinds of interrupts are supported: ? internal interrupts generated by on-chip processes ? external interrupts generated by external peripheral devices ? quasi-interrupts used for edge detection and as clock sources table 8-1. interrupt types and corresponding port pin(s) interrupt type interrupt name corresponding port pin external interrupts int1, int4 p1.1, p1.3 internal interrupts int0 (note), intb, intt0, intt1 not applicable quasi-interrupts int2 p1.2, ks0?ks7 intw not applicable note: int0 is dedicated to caller id interrupt.
interrupts s3p7588x 8- 2 vectored interrupts interrupt requests may be processed as vectored interrupts in hardware, or they can be generated by program software. a vectored interrupt is generated when the following flags and register settings, corresponding to the specific interrupt ( intn) are set to logic one: ? interrupt enable flag ( iex) ? interrupt master enabl e flag (ime) ? interrupt request flag ( irqx) ? interrupt status flags (is0, is1) ? interrupt priority register (ipr) if all conditions are satisfied for the execution of a requested service routine, the start address of the interrupt is loaded into the program counter and the program starts executing the service routine from this address. emb and erb flags for ram memory banks and registers are stored in the vector address area of the rom during interrupt service routines. the flags are stored at the beginning of the program with the vent instruction. the initial flag values determine the vectors for resets and interrupts. enable flag values are saved during the main routine, as well as during service routines. any changes that are made to enable flag values during a service routine are not stored in the vector address. when an interrupt occurs, the enable flag values before the interrupt is initiated are saved along with the program status word (psw), and the enable flag values for the interrupt is fetched from the respective vector address. then, if necessary, you can modify the enable flags during the interrupt service routine. when the interrupt service routine is returned to the main routine by the iret instruction, the original values saved in the stack are restored and the main program continues program execution with these values. software-generated interrupts to generate an interrupt request from software, the program manipulates the appropriate irqx flag. when the interrupt request flag value is set, it is retained until all other conditions for the vectored interrupt have been met, and the service routine can be initiated. multiple interrupts by manipulating the two interrupt status flags (is0 and is1), you can control service routine initialization and thereby process multiple interrupts simultaneously. if more than four interrupts are being processed at one time, you can avoid possible loss of working register data by using the push rr instruction to save register contents to the stack before the service routines are executed in the same register bank. when the routines have executed successfully, you can restore the register contents from the stack to working memory using the pop instruction. power-down mode release an interrupt can be used to release power-down mode (stop or idle). interrupts for power-down mode release are initiated by setting the corresponding interrupt enable flag. even if the ime flag is cleared to zero, power-down mode will be released by an interrupt request signal when the interrupt enable flag has been set. in such cases, the interrupt routine will not be executed since ime = "0".
s3p7588x interrups 8- 3 no no retain value until iex = 1 retain value until iex = 1 no interrupt is generated (int xx) iex = 1? ime = 1? is1, 0 = 0, 0? is1, 0 = 0, 1? request flag (irqx) 1 generate corresponding vector interrupt and release power-down mode store contents of pc and psw in the stack area; set pc contents to corresponding vector address high-priority interrupt are both interrupt sources of shared vector address used? is1, 0 = 1, 0 retain value until interrupt service routine is completed no irqx flag value remains 1 jump to interrupt start address verify interrupt source and clear irqx with a btstz instruction reset corresponding irqx flag jump to interrupt start address is1, 0 = 0, 1 yes no yes yes yes yes no yes figure 8-1. interrupt execution flowchart
interrupts s3p7588x 8- 4 ime ipr is1 is0 vector interrupt generator @ = edge detection circuit power-down mode release signal interrupt control unit intt1 intw irq4 irq0 irq1 irqt0 irqt1 irqw irq2 intb @ imod0 imod1 int4 int0 int1 @ intt0 irqb ie2 iew iet1 iet0 ie1 ie0 ie4 ieb selector imod2 int2 ks0 ~ ks7 figure 8-2. interrupt control circuit diagram
s3p7588x interrups 8- 5 ime ipr is1 is0 vector interrupt generator @ = edge detection circuit power-down mode release signal interrupt control unit intt1 intw irq0 irqt0 irqt1 irqw irq2 intb @ imod0 int0 intt0 irqb ie2 iew iet1 iet0 ie0 ieb selector imod2 ks0 ~ ks7 figure 8-3. interrupt control circuit diagram
interrupts s3p7588x 8- 6 multiple interrupts the interrupt controller can service multiple interrupts in two ways: as two-level interrupts, where either all interrupt requests or only those of highest priority are serviced, or as multi-level interrupts, when the interrupt service routine for a lower-priority request is accepted during the execution of a higher priority routine. two-level interrupt handling two-level interrupt handling is the standard method for processing multiple interrupts. when the is1 and is0 bits of the psw (fb0h.3 and fb0h.2, respectively) are both logic zero, program execution mode is normal and all interrupt requests are serviced (see figure 8-3). whenever an interrupt request is accepted, is1 and is0 are incremented by one ("0" ? "1" or "1" ? "0"), and the values are stored in the stack along with the other psw bits. after the interrupt routine has been serviced, the modified is1 and is0 values are automatically restored from the stack by an iret instruction. is0 and is1 can be manipulated directly by 1-bit write instructions, regardless of the current value of the enable memory bank flag (emb). before you can modify an interrupt status flag, however, you must first disable interrupt processing with a di instruction. when is1 = "0" and is0 = "1", all interrupt service routines are inhibited except for the highest priority interrupt currently defined by the interrupt priority register (ipr). high level interrupt generated normal program processing (status 0) set ipr int enable int disable high or low level interrupt processing (status 1) high level interrupt processing (status 2) low or high level interrupt generated figure 8-4. two-level interrupt handling
s3p7588x interrups 8- 7 multi-level interrupt handling with multi-level interrupt handling, a lower-priority interrupt request can be executed while a high-priority interrupt is being serviced. this is done by manipulating the interrupt status flags, is0 and is1 (see table 8-2). when an interrupt is requested during normal program execution, interrupt status flags is0 and is1 are set to "1" and "0", respectively. this setting allows only highest-priority interrupts to be serviced. when a high-priority request is accepted, both interrupt status flags are then cleared to "0" by software so that a request of any priority level can be serviced. in this way, the high- and low-priority requests can be serviced in parallel (see figure 8-4). table 8-2. is1 and is0 bit manipulation for multi-level interrupt handling process status before int effect of isx bit setting after int ack is1 is0 is1 is0 0 0 0 all interrupt requests are serviced. 0 1 1 0 1 only high-priority interrupts as determined by the current settings in the ipr register are serviced. 1 0 2 1 0 no additional interrupt requests will be serviced. ? ? ? 1 1 value undefined ? ? normal program processing (status 0) low or high level interrupt generated int enable low or high level interrupt generated set ipr int disable int disable modify status int enable high level interrupt generated single interrupt status 0 status 0 3-level interrupt status 2 2-level interrupt status 1 status 1 figure 8-5. multi-level interrupt handling
interrupts s3p7588x 8- 8 interrupt priority register (ipr) the 4-bit interrupt priority register (ipr) is used to control multi-level interrupt handling. its reset value is logic zero. before the ipr can be modified by 4-bit write instructions, all interrupts must first be disabled by a di instruction. fb2h ime ipr.2 ipr.1 ipr.0 by manipulating the ipr settings, you can choose to process all interrupt requests with the same priority level, or you can select one type of interrupt for high-priority processing. a low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low-priority interrupt. a high-priority interrupt cannot be interrupted by any other interrupt source. table 8-3. standard interrupt priorities interrupt default priority intb, int4 1 int0 (note) 2 int1 3 intt0 4 intt1 5 the msb of the ipr, the interrupt master enable flag (ime), enables and disables all interrupt processing. even if an interrupt request flag and its corresponding enable flag are set, a service routine cannot be executed until the ime flag is set to logic one. the ime flag can be directly manipulated by ei and di instructions, regardless of the current enable memory bank (emb) value. table 8-4. interrupt priority register settings ipr.2 ipr.1 ipr.0 result of ipr bit setting 0 0 0 normal interrupt handling according to default priority settings 0 0 1 process intb and int4 interrupts at highest priority 0 1 0 process int0 (note) interrupts at highest priority 0 1 1 process int1 interrupts at highest priority 1 0 1 process intt0 interrupts at highest priority 1 1 0 process intt1 interrupts at highest priority notes: 1. during normal interrupt processing, interrupts are processed in the order in which they occur. if two or more interrupts occur simultaneously, the processing order is determined by the default interrupt priority settings shown in table 8-3. using the ipr settings, you can select specific interrupts for high-priority processing in the event of contention. when the h igh-priority (ipr) interrupt has been processed, waiting interrupts are handled according to their default priorities. 2. int0 is dedicated to caller id interrupt.
s3p7588x interrups 8- 9 f f programming tip ? setting the int interrupt priority the following instruction sequence sets the int1 interrupt to high priority: bits emb smb 15 di ; ipr.3 (ime) ? 0 ld a,#3h ld ipr,a ei ; ipr.3 (ime) ? 1 external interrupt 0 and 1 mode registers (imod0, imod1) the following components are used to process external interrupts at the int0 (note) and int1 pin: ? edge detection circuit ? two mode registers, imod0 and imod1 the mode registers are used to control the triggering edge of the input signal. imod0 and imod1 settings let you choose either the rising or falling edge of the incoming signal as the interrupt request trigger. the int4 interrupt is an exception since its input signal generates an interrupt request on both rising and falling edges. fb4h ?0? "0" imod0.1 imod0.0 fb5h "0" "0" "0" imod1.0 imod0 and imod1 bits are addressable by 4-bit write instructions. reset clears all imod values to logic zero, selecting rising edges as the trigger for incoming interrupt requests. table 8-5. imod0 and imod1 register organization imod0 0 0 imod0.1 imod0.0 effect of imod0 settings 0 0 rising edge detection 0 1 falling edge detection 1 0 both rising and falling edge detection 1 1 irq0 flag cannot be set to "1" imod1 0 0 0 imod1.0 effect of imod1 settings 0 rising edge detection 1 falling edge detection note: int0 is dedicated to caller id interrupt, so it is unable to receive external event from int0 pin.
interrupts s3p7588x 8- 10 external interrupt 0 and 1 mode registers (continued) when a sampling clock rate of fx/64 is used for int0, an interrupt request flag must be cleared before 16 machine cycles have elapsed. edge detection imod0 irq1 imod1 irq0 edge detection p1.1 p1.0 int1 int0 figure 8-6. circuit diagram for int0 and int1 pins when modifying the imod0 and imod1 registers, it is possible to accidentally set an interrupt request flag. to avoid unwanted interrupts, take these precautions when writing your programs: 1. disable all interrupts with a di instruction. 2. modify the imod0 or imod1 register. 3. clear all relevant interrupt request flags. 4. enable the interrupt by setting the appropsriate iex flag. 5. enable all interrupts with an ei instructions.
s3p7588x interrups 8- 11 external interrupt 2 mode register (imod2) the mode register for external interrupts at the ks0?kks7 pins, imod2, is addressable only by 4-bit write instructions. reset clears all imod2 bits to logic zero. fb6h "0" "0" imod2.1 imod2.0 when imod2 is cleared to logic zero, int2 uses the rising edge of an incoming signal as the interrupt request trigger. if a rising edge is detected at the int2 pin, or when a falling edge is detected at any one of the pins ks0? ks7, the irq2 flag is set to logic one and a release signal for power-down mode is generated. table 8-6. imod2 register bit settings imod2 0 0 imod2.1 imod2.0 effect of imod2 settings 0 0 select rising edge at int2 pin (note) 0 1 select falling edge at ks4?ks7 1 0 select falling edge at ks2?ks7 1 1 select falling edge at ks0?ks7
interrupts s3p7588x 8- 12 rising edge detection circuit int2 imod2 p7.3/ks7 p7.2/ks6 p7.1/ks5 p7.0/ks4 p6.3/ks3 p6.2/ks2 p6.1/ks1 p6.0/ks0 falling edge detection circuit clock selector irq2 note : to generate a key interrupt on a falling edge at ks0 - ks7 pins must be configured to the input mode. particularly, the ks4 - ks7 must always be configured to the input mode. figure 8-7. circuit diagram for int2 and ks0?ks7 pins
s3p7588x interrups 8- 13 f f programming tip ? using int2 as a key input interrupt when the int2 interrupt is used as a key interrupt, the selected key interrupt source pin must be set to input: 1. when ks0?ks7 are selected (eight pins): bits emb smb 15 ld a, #3h ld imod2, a ; (imod2) ? #3h, ks0?ks7 falling edge select ld ea, # 00h ld pmg3, ea ; p6, 7 ? input mode ld a, #3h ld pumod2, a ; enable p6 and p7 pull-up resistors 2. when ks2?ks7 are selected (six pins): bits emb smb 15 ld a, #2h ld imod2, a ; (imod2) ? #2h, ks2?ks7 falling edge select ld ea, #03h ld pmg3, ea ; p7, p6.2?p6.3 ? input mode ld a, #3h ld pumod2, a ; enable p6 and p7 pull-up resistors 3. when ks4?ks7 are selected (four pins), p7 must be specified as a key strobe signal input: bits emb smb 15 ld a, #1h ld imod2, a ; (imod2) ? #1h, ks4?ks7 falling edge select ld ea, #0fh ld pmg3, ea ld a, #2 ld pumod2, a ; enable p7 pull-up resistor
interrupts s3p7588x 8- 14 interrupt flags there are three types of interrupt flags: interrupt request and interrupt enable flags that correspond to each interrupt, the interrupt master enable flag, which enables or disables all interrupt processing. interrupt master enable flag (ime) the interrupt master enable flag, ime, enables or disables all interrupt processing. therefore, even when an irqx flag is set and its corresponding iex flag is enabled, the interrupt service routine is not executed until the ime flag is set to logic one. the ime flag is located in the ipr register (ipr.3). it can be directly manipulated by ei and di instructions, regardless of the current value of the enable memory bank flag (emb). ime ipr.2 ipr.1 ipr.0 effect of bit settings 0 inhibit all interrupts 1 enable all interrupts interrupt enable flags ( iex) iex flags, when set to logical one, enable specific interrupt requests to be serviced. when the interrupt request flag is set to logic one, an interrupt will not be serviced until its corresponding iex flag is also enabled. interrupt enable flags can be read, written, or tested directly by 1-bit instructions (bits and bitr) or 4-bit instructions. iex flags can be addressed directly at their specific ram addresses, despite the current value of the enable memory bank (emb) flag. table 8-7. interrupt enable and interrupt request flag addresses address bit 3 bit 2 bit 1 bit 0 fb8h ie4 irq4 ieb irqb fbah 0 0 iew irqw fbbh 0 0 iet1 irqt1 fbch 0 0 iet0 irqt0 fbeh ie1 irq1 ie0 irq0 fbfh 0 0 ie2 irq2 notes: 1. iex refers generically to all interrupt enable flags. 2. irqx refers generically to all interrupt request flags. 3. iex = 0 is interrupt disable mode. 4. iex = 1 is interrupt enable mode.
s3p7588x interrups 8- 15 interrupt request flags ( irqx) interrupt request flags, are read/write addressable by 1-bit or 4-bit instructions. irqx flags can be addressed directly at their specific ram addresses, regardless of the current value of the enable memory bank (emb) flag. when a specific irqx flag is set to logic one, the corresponding interrupt request is generated. the flag is then automatically cleared to logic zero when the interrupt has been serviced. exceptions are the watch timer interrupt request flags, irqw, and the external interrupt 2 flag irq2, which must be cleared by software after the interrupt service routine has executed. irqx flags are also used to execute interrupt requests from software. in summary, follow these guidelines for using irqx flags: 1. irqx is set to request an interrupt when an interrupt meets the set condition for interrupt generation. 2. irqx is set to "1" by hardware and then cleared by hardware when the interrupt has been serviced (with the exception of irqw and irq2). 3. if irqx is set to "1" by software, an interrupt is also generated. when two interrupts share the same service routine start address, interrupt processing may occur in one of two ways: ? when only one interrupt is enabled, the irqx flag is cleared automatically when the interrupt has been serviced. ? when two interrupts are enabled, the request flag is not automatically cleared so that the user has an opportunity to locate the source of the interrupt request. in this case, the irqx setting must be cleared manually using a btstz instruction. table 8-8. interrupt request flag conditions and priorities interrupt source internal / external pre-condition for irqx flag setting interrupt priority irq flag name intb i reference time interval signal from basic timer 1 irqb int4 e both rising and falling edges detected at int4 1 irq4 int0 (note2) i falling edge detected at caller id interrupt 2 irq0 int1 e rising or falling edge detected at int1 pin 3 irq1 intt0 i signals for tcnt0 and tref0 registers match 5 irqt0 intt1 i signals for tcnt1 and tref1 registers match 6 irqt1 int2 e rising edge detected at int2 pin or else a falling edge is detected at any of the ks0?ks7 pins ? irq2 intw i time interval of 0.5 secs or 3.19 msecs ? irqw notes: 1. the quasi-interrupt int2 is only used for testing incoming signals. 2. int0 is dedicated to caller id interrupt, and must be programmed as falling edge detection mode.
interrupts s3p7588x 8- 16 f f programming tip ? enabling the intb and int4 interrupts to simultaneously enable intb and int4 interrupts: intb di btstz irqb ; irqb = 1 ? jr int4 ; if no, int4 interrupt; if yes, intb interrupt is processed ? ? ? ei iret int4 bitr irq4 ; int4 is processed ? ? ? ei iret
s3p7588x power-down 9- 1 9 power-down overview the s3p7588x microcontroller has two power-down modes to reduce power consumption: idle and stop. idle mode is initiated by the idle instruction and stop mode by the instruction stop. (several nop instructions must always follow an idle or stop instruction in a program.) in idle mode, the cpu clock stops while peripherals and the oscillation source continue to operate normally. when reset occurs during normal operation or during a power-down mode, a reset operation is initiated and the cpu enters idle mode. when the standard oscillation stabilization time interval (31.3ms at 4.19mhz) has elapsed, normal cpu operation resumes. in stop mode, system clock oscillation is halted (assuming it is currently operating), and peripheral hardware components are powered-down. the effect of stop mode on specific peripheral hardware components ? cpu, basic timer, timer/counters, and watch-timer ? and on external interrupt requests, is detailed in table 9-1. note do not use stop mode if you are using an external clock source because x in input must be restricted internally to v ss to reduce current leakage. idle or stop modes are terminated either by a reset , or by an interrupt with the exception of int0, which are enabled by the corresponding interrupt enable flag, iex. when power-down mode is terminated by reset input, a normal reset operation is executed. assuming that both the interrupt enable flag and the interrupt request flag are set to "1", power-down mode is released immediately upon entering power-down mode. when an interrupt is used to release power-down mode, the operation differs depending on the value of the interrupt master enable flag (ime): ? if the ime flag = "0", program execution is started immediately after the instruction which issues the request to enter power-down mode. the interrupt request flag remains set to logic one. ? if the ime flag = "1", two instructions are executed after the power-down mode release. then, the vectored interrupt is initiated. however, when the release signal is caused by int2 or intw, the operation is identical to the ime = 0 condition. that is, a vector interrupt is not generated.
power-down s3p7588x 9- 2 table 9-1. hardware operation during power-down modes operation stop mode (stop) idle mode (idle) clock oscillator system clock oscillation stops cpu clock oscillation stops. (system clock oscillation continues) basic timer basic timer stops basic timer operates. (with irqb set at each reference interval) caller id caller id stops except lr detector. to save power consumption of 14bit adc, user must set the additional mode register in caller id module (refer to chapter 7) caller id operates. caller id can be stopped by setting the mode register in caller id module (refer to chapter 7) timer/counter 0 operates only if tcl0 is selected as the counter clock timer/counter 0 operates timer/counter 1 operates only if tcl1 is selected as the counter clock timer/counter 1 operates watch timer watch timer operation is stopped watch timer operates external interrupts int0, int1, int2, and int4 are acknowledged. (caller id?s lr interrupt can wake up system clock through int0 interrupt) int0, int1, int2, and int4 are acknowledged. (any interrupt of caller id can wake up cpu through int0 interrupt) cpu all cpu operations are disabled all cpu operations are disabled power-down mode release signal interrupt request signals are enabled by an interrupt enable flag or by reset input interrupt request signals are enabled by an interrupt enable flag or by reset input idle mode timing diagrams oscillator stabilization (36.6 ms/3.58 mhz) reset idle istruction normal mode idle mode normal mode clock signal normal oscillation figure 9-1. timing when idle mode is released by reset reset
s3p7588x power-down 9- 3 clock signal normal oscillation mode release signal idle istruction interrupt acknowledge (ime = 1) normal mode idle mode normal mode figure 9-2. timing when idle mode is released by an interrupt stop mode timing diagrams oscillator stabilization (36.6 ms/3.58 mhz) reset stop instruction normal mode normal mode clock signal stop mode idle mode oscillation stops oscillation resumes figure 9-3. timing when stop mode is released by reset reset oscillator stabilization (bmod setting) stop instruction normal mode normal mode clock signal stop mode idle mode oscillation stops oscillation resumes mode release signal int ack (ime = 1) figure 9-4. timing when stop mode is release by an interrupt
power-down s3p7588x 9- 4 port pin configuration for power-down the following method describes how to configure i/o port pins to reduce power consumption during power-down modes (stop, idle): condition 1: if the microcontroller is not configured to an external device: 1. connect unused port pins according to the information in table 9-2. 2. disable all pull-up resistors for output pins by m aking the appropriate modifications to the pull-up resistor mode register, pumod. reason: if output goes low when the pull-up resistor is enabled, there may be unexpected surges of current through the pull-up. 3. disable pull-up resistors for input pins configured to v dd or v ss levels in order to check the current input option. reason: if the input level of a port pin is set to v ss when a pull-up resistor is enabled, it will draw an unnecessarily large current. condition 2: if the microcontroller is configured to an external device and the external device's v dd source is turned off in power-down mode. 1. connect unused port pins according to the information in table 9-2. 2. disable the pull-up resistors of output pins by making the appropriate modifications to the pull-up resistor mode register, pumod. reason: if output goes low when the pull-up resistor is enabled, there may be unexpected surges of current through the pull-up. 3. disable pull-up resistors for input pins configured to v dd or v ss levels in order to check the current input option. reason: if the input level of a port pin is set to v ss when a pull-up resistor is enabled, it will draw an unnecessarily large current. 4. disable the pull-up resistors of input pins connected to the external device by making the necessary modifications to the pumod register. 5. configure the output pins that are connected to the external device to low level. reason: when the external device's v dd source is turned off, and if the microcontroller's output pins are set to high level, v dd ? 0.7v is supplied to the v dd of the external device through its input pin. this causes the device to operate at the level v dd ? 0.7v. in this case, total current consumption would not be reduced. 6. determine the correct output pin state necessary to block current pass in according with the external transistors (pnp, npn).
s3p7588x power-down 9- 5 recommended connections for unused pins to reduce overall power consumption, please configure unused pins according to the guidelines described in table 9-2. table 9-2. unused pin connections for reduced power consumption pin/share pin names recommended connection p1.1 / int1 ?p 1.2 / int2 connect to v dd p1.3 / int4 p2.0 / tclo0 p2.3 / buz p3.0 / tcl0 p3.1 / tcl1 p3.2 p3.3 p4.0 / btco p4.1?p4.3 p5.0?p5.3 p6.0 / ks0?p6.3 / ks3 p7.0 / ks4?p7.3 / ks7 p9.0 p9.1 / tclo1 p9.2 / clo input mode: connect to v dd output mode: no connection dtmf no connection vref, out no connection ins, inn, inp, lrin connect to v ss nc connect to v ss
power-down s3p7588x 9- 6 notes
s3p7588x reset reset 10- 1 10 reset reset overview when a reset signal is input during normal operation or power-down mode, a hardware reset operation is initiated and the cpu enters idle mode. then, when the standard oscillation stabilization interval of 36.6 ms at 3.58 mhz has elapsed, normal system operation resumes. regardless of when the reset occurs ? during normal operating mode or during a power-down mode ? most hardware register values are set to the reset values described in table 10-1 below. the current status of several register values is, however, always retained when a reset occurs during idle or stop mode; if a reset occurs during normal operating mode, their values are undefined. current values that are retained in this case are as follows: ? carry flag ? general-purpose registers e, a, l, h, x, w, z, and y oscillator stabilization (36.6 ms/3.58 mhz) operating mode idle mode reset operation normal mode or power-down mode reset input figure 10-1. timing for oscillation stabilization after reset reset caller id reset signal caller id receiver has the dedicated reset signal that is come from the output of p8.0 or p3.1. whichever port you choose, you should make the active-low reset pulse (high ? low ? high) at the start of the program, or the caller id receiver remains reset state regardless of the reset signal. p8 is a internal redundant port and not used for external interface, so it is recommended to use p8.0 as caller id receiver reset signal. to use p8.0, set p8.1 as 1 ahead. (refer to chapter 7)
reset reset s3p7588x 10- 2 hardware reset values after reset reset table 10-1 gives you detailed information about hardware register values after a reset occurs during power- down mode or during normal operation. table 10-1. hardware register values after reset reset hardware component or subcomponent if reset reset occurs during power-down mode if reset reset occurs during normal operation program counter (pc) lower five bits of address 0000h are transferred to pc12?8, and the contents of 0001h to pc7?0. lower five bits of address 0000h are transferred to pc12?8, and the contents of 0001h to pc7?0. program status word (psw): carry flag (c) values retained undefined skip flag (sc0?sc2) 0 0 interrupt status flags (is0, is1) 0 0 bank enable flags (emb, erb) bit 6 of address 0000h in program memory is transferred to the erb flag, and bit 7 of the address to the emb flag. bit 6 of address 0000h in program memory is transferred to the erb flag, and bit 7 of the address to the emb flag. stack pointer (sp) undefined undefined data memory (ram): general registers e, a, l, h, x, w, z, y values retained undefined general-purpose registers values retained (1) undefined bank selection registers (smb, srb) 0, 0 0, 0 bsc register (bsc0?bsc) 0 0 clocks: power control register (pcon) 0 0 clock output mode register (clmod) 0 0 interrupts: interrupt request flags ( irqx) 0 0 interrupt enable flags ( iex) 0 0 interrupt priority flag (ipr) 0 0 interrupt master enable flag (ime) 0 0 int0 mode register (imod0) 0 0 int1 mode register (imod1) (2) 0 0 int2 mode register (imod2) 0 0 note: the value of the 0f8h?0fdh are not retained when a reset signal is input.
s3p7588x reset reset 10- 3 table 10-1. hardware register values after reset reset (continued) hardware component or subcomponent if reset occurs during power-down mode if reset occurs during normal operation i/o ports: output buffers off off output latches 0 0 port mode flags (pmg) 0 0 pull-up resistor mode reg (pumod1/2) 0 0 port open-drain enable register (pne1) 0 0 basic timer: count register (bcnt) undefined undefined mode register (bmod) 0 0 output enable flag (boe) 0 0 timer/counters 0 and 1: count registers (tcnt0/1) 0 0 reference registers (tref0/1) ffh/ffh ffh/ffh mode registers (tmod0/1) 0 0 t/c output enable flags (toe0/1) 0 0 t/c output latch (tol0/1) 0 0 watch timer: watch timer mode register(wmod) 0 0 watchdog timer wdt mode register (wdmod) a5h a5h wdt clear flag (wdtcf) 0 0 dtmf generator: dtmf mode register (dtmr) 0 0 caller id all registers 0 0
reset reset s3p7588x 10- 4 notes
s3p7588x i/o ports 11- 1 11 i/o ports overview the s3p7588x has one input port and seven i/o ports. pin addresses for all i/o ports are mapped in bank 15 of the ram. the contents of i/o port pin latches can be read, written, or tested at the corresponding address using bit manipulation instructions. s3p7588x has three input pins and 25 configurable i/o pins for a maximum number of 28 i/o pins. port mode flags port mode flags (pm) are used to configure i/o ports 2 and 3 (port mode group 1), ports 4 and 5 (port mode group 2), ports 6 and 7 (port mode group 3), and port 8 and 9 (port mode group 4) to input or output mode by setting or clearing the corresponding i/o buffer. pmg flags are grouped in four 8-bit registers, and are addressable by 8-bit write instructions only. pumod control register the pull-up mode registers, pumod1 and 2 are 8-bit and 4-bit registers, respectively, used to assign internal pull-up resistors by software to specific i/o ports. when configurable i/o ports 2 through 9 serves as an output pin, its assigned pull-up resistor is automatically disabled, even though the pin?s pull-up resistor is enabled by a corresponding bit setting in the pull-up resistor mode register (pumod). pumod1 is addressable by 8-bit write instructions only, pumod2 is addressable by 4-bit write instructions only. reset clears pumod register values to logic zero, automatically disconnecting all software- assignable port pull- up resistors. table 11-1. i/o port overview port i/o pins pin names address function description 1 i 4 p1.1?p1.3 ff1h 4-bit input port. 1-bit and 4-bit read and test is possible. 1-bit pull-up resistors are software assignable 2, 3 i/o 8 p2.0, p2.3 (note) p3.0?p3.3 ff2h ff3h 4-bit i/o ports. 1-bit and 4-bit read/write/test is possible. ports 2 and 3 pins are individually software configurable as input or output. 4-bit pull-up resistors are software assignable; pull-up registers are automatically disabled for output pins. ports 2 and 3 can be paired for 8-bit data transfer. note: p2.1, p2.2 is dedicated to interface with caller id, and unable to be used from outside chip. (refer chapter 7)
i/o ports s3p7588x 11- 2 table 11-1. i/o port overview (continued) port i/o pins pin names address function description 4, 5 i/o 8 p4.0?p4.3 p5.0?p5.3 ff4h ff5h 4-bit i/o ports. 1-bit and 4-bit read/write/test is possible. port 4 and 5 pins are individually software configurable as input or output. 4-bit pull-up resistors are software assignable; pull- up registers are automatically disable for output pins. n- ch open drain or push-pull output may be selected by software. ports 4 and 5 can be paired for 8-bit data transfer. 6, 7 i/o 8 p6.0?p6.3 p7.0?p7.3 ff6h ff7h 4-bit i/o ports. 1-bit and 4 -bit read/write/test is possible. port 6 and 7 pins are individually software configurable as input or output. 4-bit pull -up resistors are software assignable; pull-up registers are automatically disabled for output pins. ports 6 and 7 can be paired for 8-bit data transfer. 8, 9 (note) i/o 8 p8.0?p8.3 p9.0?p9.2 ff8h ff9h 4-bit i/o port. 1-bit and 4-bit read/write and test is possible. ports 8 and 9 pins are individually software configurable as input or output. 4-bit pull-up resistors are software assignable; pull-up registers are automatically disable for output pins. ports 8 and 9 can be paired for 8-bit data transf0er. note: port 8 is dedicated to interface with caller id, and unable to be used from outside chip. (refer chap. 7) table 11-2. port pin status during instruction execution instruction type example input mode status output mode status 1-bit test 1-bit input 4-bit input 8-bit input btst ldb ld ld p2.3 c,p1.0 a,p7 ea,p4 input or test data at each pin input or test data at output latch 1-bit output bitr p2.3 output latch contents undefined output pin status is modified 4-bit output 8-bit output ld ld p2,a p6,ea transfer accumulator data to the output latch transfer accumulator data to the output pin
s3p7588x i/o ports 11- 3 port mode flags (pm flags) port mode flags (pm) are used to configure i/o ports 2?9 to input or output mode by setting or clearing the corresponding i/o buffer. for convenient program reference, pm flags are organized into four groups ? pmg1, pmg2, pmg3, and pmg4 as shown in table 11-3. pm flags are addressable by 8-bit write instructions only. when a pm flag is ?0?, the port is set to input mode; when it is ?1?, the port is enabled for output. reset clears all port mode flags to logic zero, automatically configuring the corresponding i/o ports to input mode. table 11-3. port mode group flags pm group id address bit 3 bit 2 bit 1 bit 0 pmg1 fe8h pm2.3 pm2.2 pm2.1 pm2.0 fe9h pm3.3 pm3.2 pm3.1 pm3.0 pmg2 feah pm4.3 pm4.2 pm4.1 pm4.0 febh pm5.3 pm5.2 pm5.1 pm5.0 pmg3 fech pm6.3 pm6.2 pm6.1 pm6.0 fedh pm7.3 pm7.2 pm7.1 pm7.0 pmg4 feeh pm8.3 pm8.2 pm8.1 pm8.0 fefh ?0? pm9.2 pm9.1 pm9.0 note: if bit = ?0?, the corresponding i/o pin is set to input mode. if bit = ?1?, the pin is set to output mode: pm4 for port 4 and so on. all flags are cleared to ?0? following reset . f f programming tip ? configuring i/o ports to input or output configure p2.3 and p3 as an output port and the other ports as input ports: bits emb smb 15 ld ea,#0f8h ld pmg1,ea ; p2.3, p3 ? ? input ea,#00h pmg2,ea p4, p5 ld ; ? input pmg4,ea p8, p9
i/o ports s3p7588x 11- 4 the pull-up resistor mode registers (pumod1 and 2) are 8-bit registers used to assign internal pull-up resistors by software to specific i/o ports. disabled, even though the pin?s pull-up is enabled by a corresponding pumod bit setting. pumod1 is addressable by 8-bit write instructions only. pumod2 is addressable by 4bit write instructions only. clears pumod register values to logic zero, automatically disconnecting all software- assignable port pull- table 11-4. pull-up resistor mode register (pumod) organization address bit 3 bit 1 bit 0 fdch pur1.3 pur1.1 pur1.0 pur5 pur4 pur2 pumod2 pur9 pur8 pur6 note: port 2, and so on. f f programming tip ? enabling and disabling i/o port pull-up resistors p2?p5 enable pull-up resistors, p1 disable pull-up resistors. bits emb smb 15 ld ea,#0f0h ld pumod1,ea ; p2?p5 enable n-channel open-drain mode register (pne) the n-channel, open-drain mode register (pne) is used to configure ports 4 and 5 to n-channel open-drain or as push-pull outputs. when a bit in the pne register is set to "1", the corresponding output pin is configured to n-channel open-drain; when set to "0", the output pin is configured to push-pull. the pne register consists of an 8-bit register; pne1 can be addressed by 8-bit write instructions only. fdah pne4.3 pne4.2 pne4.1 pne4.0 pne1 fdbh pne5.3 pne5.2 pne5.1 pne5.0
s3p7588x i/o ports 11- 5 port 1 circuit diagram pur1.1 pur1.2 pur1.3 v dd v dd v dd int1 int2 int3 p1.1 / int1 p1.2 / int2 p1.3 / int4 figure 11-1. port 1 circuit diagram
i/o ports s3p7588x 11- 6 port 2, 3, 6, 7, 8, and 9 circuit diagram output latch mux 1, 4, 8 v dd purx purx purx purx pmx.0 pmx.1 pmx.2 pmx.3 note : when a port pin acts as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings to the pull-up resistor mode register (pumod). px.0 px.1 px.2 px.3 x = port number (2, 3, 6, 8) 1, 4, 8 figure 11-2. port 2, 3, 6, 7, 8, and 9 circuit diagram
s3p7588x i/o ports 11- 7 port 4, 5 circuit diagram mux 8 v dd pumod.b px.b 8 pne output latch pmx.b 1, 4, 8 8 x = 4, 5 b = 0, 1, 2, 3 n-ch p-ch p-ch v ss b = 4, 5 figure 11-3. port 4 and 5 circuit diagram
i/o ports s3p7588x 11- 8 notes
s3p7588x timers and timer/counters 12- 1 12 timers and timer/counters overview the s3p7588x microcontroller has four timer and timer/counter modules: ? 8-bit basic timer (bt) ? 8-bit timer/counters (tc0, tc1) ? watch timer (wt) the 8-bit basic timer (bt) is the microcontroller's main interval timer. it generates an interrupt request at a fixed time interval when the appropriate modification is made to its mode register. when the contents of the basic timer counter register bcnt overflows, a pulse is output to the basic timer output pin, btco. the basic timer also functions as a 'watchdog' timer and is used to determine clock oscillation stabilization time when stop mode is released by an interrupt and after a reset . the 8-bit timer/counters (tc0, tc1) are programmable timer/counters that are used primarily for event counting and for clock frequency modification and output. the watch timer (wt) module consists of an 8-bit watch timer mode register, a clock selector, and a frequency divider circuit. watch timer functions include real-time and watch-time measurement, system clock interval timing, buzzer output generation.
timers and timer/counters s3p 7588x 12- 2 basic timer (bt) overview the 8-bit basic timer (bt) has six functional components: ? clock selector logic ? 4-bit mode register (bmod) ? 8-bit counter register (bcnt) ? output enable flag (boe) ? 8-bit watchdog timer mode register (wdmod) ? watchdog timer counter clear flag (wdtcf) the basic timer generates interrupt requests at precise intervals, based on the frequency of the system clock. timer pulses are output from the basic timer's counter register bcnt to the output pin btco when an overflow occurs in the counter register bcnt. you can use the basic timer as a "watchdog" timer for monitoring system events or use bt output to stabilize clock oscillation when stop mode is released by an interrupt and following reset . bit settings in the basic timer mode register bmod turns the bt module on and off, selects the input clock frequency, and controls interrupt or stabilization intervals. interval timer function the basic timer's primary function is to measure elapsed time intervals. the standard time interval is equal to 256 basic timer clock pulses. to restart the basic timer, one bit setting is required: bit 3 of the mode register bmod should be set to logic one. the input clock frequency and the interrupt and stabilization interval are selected by loading the appropriate bit values to bmod.2?bmod.0. the 8-bit counter register, bcnt, is incremented each time a clock signal is detected that corresponds to the frequency selected by bmod. bcnt continues incrementing as it counts bt clocks until an overflow occurs ( 3 255). an overflow causes the bt interrupt request flag (irqb) to be set to logic one to signal that the designated time interval has elapsed. an interrupt request is than generated, bcnt is cleared to logic zero, and counting continues from 00h. watchdog timer function the basic timer can also be used as a "watchdog" timer to signal the occurrence of system or program operation error. for this purpose, instruction that clear the watchdog timer (bits wdtcf) should be executed at proper points in a program within given period. if an instruction that clears the watchdog timer is not executed within the given period and the watchdog timer overflows, reset signal is generated and the system restarts with reset status. an operation of watchdog timer is as follows: ? write some values (except #5ah) to watchdog timer mode register, wdmod ? if wdcnt overflows, system reset is generated.
s3p7588x timers and timer/counters 12- 3 oscillation stabilization interval control bits 2?0 of the bmod register are used to select the input clock frequency for the basic timer. this setting also determines the time interval (also referred to as ?wait time?) required to stabilize clock signal oscillation when stop mode is released by an interrupt. when a reset signal is inputted, the standard stabilization interval for system clock oscillation following the reset is 31.3 ms at 4.19mhz. table 12-1. basic timer register overview register name type description size ram address addressing mode reset value bmod control controls the clock frequency (mode) of the basic timer; also, the oscillation stabilization interval after stop mode release or reset 4-bit f85h 4-bit write-only; bmod.3: 1-bit writeable ?0? bcnt counter counts clock pulses matching the bmod frequency setting 8-bit f86h?f87h 8-bit read-only u (note) boe flag controls output of basic timer output latch to the btco pin 1-bit f92h.1 1-, 4-bit read/write ?0? wdmod control controls watchdog timer operation. 8-bit f98h?f99h 8-bit write-only a5h wdtcf control clears the watchdog timer?s counter. 1-bit f9ah.3 1-, 4-bit write-only ?0? note: 'u' means the value is undetermined after a reset .
timers and timer/counters s3p 7588x 12- 4 wait means stabilization time after reset or stabilization time after stop mode release. the reset signal can be generated if the wdmod is toggled for 8 times where "toggle" means change from 5ah to an other value, and vice versa. notes : 1. 2. bmod.3 bmod.2 bmod.1 bmod.0 bits instruction overflow clear bcnt "clear" signal 1 pulse period = bt input clock 2 8 (1/2 duty) interrupt request clear irqb cpu clock start signal (power-down release) wait (note 1) 3-bit counter clear overflow reset bits instruction reset wdtcf clock selector wdcnt wdmod (note 2) reset generation delay clear stop 8 8 bcnt irqb 1-bit r/w clock input 4 boe p4.0 latch btco/p4.0 figure 12-1. basic timer circuit diagram
s3p7588x microcontroller ( preliminary ) timers and timer/counters 12- 5 basic timer mode register (bmod) the basic timer mode register, bmod, is a 4-bit write-only register. bit 3, the basic timer start control bit, is also 1-bit addressable. all bmod values are set to logic zero following reset and interrupt request signal generation is set to the longest interval. (bt counter operation cannot be stopped.) bmod settings have the following effects: ? restart the basic timer; ? control the frequency of clock signal input to the basic timer; ? determine time interval required for clock oscillation to stabilize following the release of stop mode by an interrupt. by loading different values into the bmod register, you can dynamically modify the basic timer clock frequency during program execution. four bt frequencies, ranging from fx/2 12 to fx/2 5 , are selectable. since bmod's reset value is logic zero, the default clock frequency setting is fx/2 12 . the most significant bit of the bmod register, bmod.3, is used to restart the basic timer. when bmod.3 is set to logic one by a 1-bit write instruction, the contents of the bt counter register (bcnt) and the bt interrupt request flag (irqb) are both cleared to logic zero, and timer operation restarts. the combination of bit settings in the remaining three registers ? bmod.2, bmod.1, and bmod.0 ? determine the clock input frequency and oscillation stabilization interval. table 12-2. basic timer mode register (bmod) organization bmod.3 basic timer start control bit 1 start basic timer; clear irqb, bcnt, and bmod.3 to "0" bmod.2 bmod.1 bmod.0 basic timer input clock oscillation stabilization 0 0 0 fx/2 12 (1.02khz) 2 20 / fx (250ms) 0 1 1 fx/2 9 (8.18khz) 2 17 / fx (31.3ms) 1 0 1 fx/2 7 (32.7khz) 2 15 / fx (7.82ms) 1 1 1 fx/2 5 (131khz) 2 13 / fx (1.95ms) notes: 1. clock frequencies and oscillation stabilization assume a system oscillator clock frequency (fx) of 4.19mhz. 2. fx = system clock frequency. 3. oscillation stabilization time is the time required to stabilize clock signal oscillation after stop mode is released. the data in the table column 'oscillation stabilization' can also be interpreted as "interrupt interval time." 4. the standard stabilization time for system clock oscillation following a reset is 31.3 ms at 4.19mhz.
timers and timer/counters s3p 7588x 12- 6 basic timer counter (bcnt) bcnt is an 8-bit counter for the basic timer. it can be addressed by 8-bit read instructions. reset leaves the bcnt counter value undetermined. bcnt is automatically cleared to logic zero whenever the bmod register control bit (bmod.3) is set to "1" to restart the basic timer. it is incremented each time a clock pulse of the frequency determined by the current bmod bit settings is detected. when bcnt has incrementing to hexadecimal ?ffh? ( 3 255 clock pulses), it is cleared to ?00h? and an overflow is generated. the overflow causes the interrupt request flag, irqb, to be set to logic one. when the interrupt request is generated, bcnt immediately resumes counting incoming clock signals. note always execute a bcnt read operation twice to eliminate the possibility of reading unstable data while the counter is incrementing. if, after two consecutive reads, the bcnt values match, you can select the latter value as valid data. until the results of the consecutive reads match, however, the read operation must be repeated until the validation condition is met. basic timer output enable flag (boe) the basic timer output enable flag (boe) enables and disables basic timer output to the btco pin at i/o port 4 (p4.0). when boe is logic zero, basic timer output to the btco pin is disabled; when it is logic one, bt output to the btco pin is enabled. a reset clears the boe flag to "0", disabling basic timer output to the btco pin. when the boe flag is set to "1" and the bcnt register overflows, the overflow signal is sent to the btco pin. boe can be addressed by 1 -bit read and write instructions. bit 3 bit 2 bit 1 bit 0 f92h toe1 toe0 boe 0 basic timer operation sequence the basic timer's sequence of operations may be summarized as follows: 1. set bmod.3 to logic one to restart the basic timer 2. bcnt is then incremented by one after each clock pulse corresponding to bmod selection 3. bcnt overflows if bcnt = 255 (bcnt = ffh) 4. when an overflow occurs, the irqb flag is set by hardware to logic one 5. the interrupt request is generated 6. bcnt is then cleared by hardware to logic zero 7. basic timer resumes counting clock pulses
s3p7588x microcontroller ( preliminary ) timers and timer/counters 12- 7 f f programming tip ? using the basic timer 1. to read the basic timer count register (bcnt): bits emb smb 15 bcntr ld ea,bcn t ld yz,ea ld ea,bcnt cpse ea,yz jr bcntr 2. when stop mode is released by an interrupt, set the oscillation stabilization interval to 31.3ms: bits emb smb 15 ld a,#0bh ld bmod,a ; wait time is 31.3ms stop ; set stop power-down mode nop nop nop normal operating mode stop mode cpu operation idle mode normal operating mode stop instruction stop mode is released by interrupt (31.3ms) 3. to set the basic timer interrupt interval time to 1.95ms (at 4.19mhz): bits emb smb 15 ld a,#0fh ld bmod,a ei bits ieb ; basic timer interrupt enable flag is set to "1" 4. clear bcnt and the irqb flag and restart the basic timer: bits emb smb 15 bits bmod.3
timers and timer/counters s3p 7588x 12- 8 watchdog timer mode register (wdmod) the watchdog timer mode register, wdmod, is a 8-bit write-only register. wdmod register controls to enable or disable the watchdog function. wdmod values are set to logic ?a5h? following reset and this value enables the watchdog timer. watchdog timer is set to the longest interval because bt overflow signal is generated with the longest interval. wdmod watchdog timer enable/disable control 5ah disable watchdog timer function any other value enable watchdog timer function watchdog timer counter (wdcnt) the watchdog timer counter, wdcnt, is a 3-bit counter. wdcnt is automatically cleared to logic zero, and restarts whenever the wdtcf register control bit is set to ?1?. reset , stop, and wait signal clears the wdcnt to logic zero also. wdcnt increments each time a clock pulse of the overflow frequency determined by the current bmod bit setting is generated. when wdcnt has incremented to hexadecimal ?07h?, it is cleared to ?00h? and an overflow is generated. the overflow causes the system reset . when the interrupt request is generated, bcnt immediately resumes counting incoming clock signals. watchdog timer counter clear flag (wdtcf) the watchdog timer counter clear flag, wdtcf, is a 1-bit write instruction. when wdtcf is set to one, it clears the wdcnt to zero and restarts the wdcnt. wdtcf register bits 2?0 are always logic zero. table 12-3. watchdog timer interval time bmod bt input clock wdcnt input clock wdt interval time main clock x000b 212/fx 212/fx 28 212/fx 28 23 2 second x011b 29/fx 29/fx 28 29/fx 28 23 250 ms x101b 27/fx 27/fx 28 27/fx 28 23 62.5 ms x111b 25/fx 25/fx 28 25/fx 28 23 15.6 ms notes: 1. clock frequencies assume a system oscillator clock frequency (fx) of 4.19mhz 2. fx = system clock frequency.
s3p7588x microcontroller ( preliminary ) timers and timer/counters 12- 9 f f programming tip ? using the watchdog timer reset di ld ea,#00h ld sp,ea ? ? ? ld a,#0dh ; wdcnt input clock is 7.82ms ld bmod,a ? ? ? main bits wdtcf ; main routine operation period must be shorter than watchdog ? ; timer?s period ? ? jp main
timers and timer/counters s3p 7588x 12- 10 8-bit timer/counters 0 and 1 (tc0, tc1) overview the s3p7588x tc0 and tc1 are identical except that they have different counter clock sources, which are controlled by the tmodn register. timer/counters 0 and 1 (tc0, tc1) are used to count system 'events' by identifying the transition (high-to-low or low-to-high) of incoming square wave signals. to indicate that an event has occurred, or that a specified time interval has elapsed, tc generates an interrupt request. by counting signal transitions and comparing the current counter value with the reference register value, tc can be used to measure specific time intervals. tc has a reloadable counter that consists of two parts: an 8-bit reference register, trefn (n = 0, 1) into which you write the counter reference value, and an 8-bit counter register , tcntn (n = 0, 1) whose value is automatically incremented by counter logic. 8-bit mode register, tmodn (n = 0, 1), is used to activate the timer/counter and to select the basic clock frequency to be used for timer/counter operations. to dynamically modify the basic frequency, new values can be loaded into the tmodn register during program execution. tc function summary 8-bit programmable timer generates interrupts at specific time intervals based on the selected clock frequency. external event counter counts various system "events" based on edge detection of external clock signals at the tc input pin, tcln (n = 0, 1). arbitrary frequency output outputs clock frequencies to the tc output pin, tclon (n = 0, 1). external signal divider divides the frequency of an incoming external clock signal according to a modifiable reference value (trefn), and outputs the modified frequency to the tclon pin.
s3p7588x microcontroller ( preliminary ) timers and timer/counters 12- 11 tc component summary mode register (tmodn) activates the timer/counter and selects the internal clock frequency or the external clock source at the tcln pin. reference register (trefn) stores the reference value for the desired number of clock pulses between interrupt requests. counter register (tcntn) counts internal or external clock pulses based on the bit settings in tmodn and trefn. clock selector circuit together with the mode register (tmodn), lets you select one of four internal clock frequencies or an external clock. 8-bit comparator determines when to generate an interrupt by comparing the current value of the counter register (tcntn) with the reference value previously programmed into the reference register (trefn). output latch (toln) when the contents of the tcntn and trefn registers coincide, the timer/counter interrupt request flag (irqtn) is set to "1", the status of toln is inverted, and an interrupt is generated. output enable flag (toen) must be set to logic one before the contents of the toln latch can be output to tclon. interrupt request flag (irqtn) cleared when tc operation starts and the tc interrupt service routine is executed and set to one whenever the counter value and reference value coincide. interrupt enable flag (ietn) must be set to logic one before the interrupt requests generated by timer/counters can be processed. table 12-4. tc register overview register name type description size ram address addressing mode reset value tmod0 tmod1 control controls tc0 and tc1 enable/disable (bit 2); clears and resumes counting operation (bit 3); sets input clock and clock frequency (bits 6?4) 8-bit f90h?f91h fa0h?fa1h 8-bit write only; (tmodn.3 is also 1 -bit writeable) "0" tcnt0 tcnt1 counter counts clock pulses matching the tmodn frequency setting 8-bit f94h?f95h fa4h?fa5h 8-bit read-only "0" tref0 tref1 reference stores reference value for the timer/counters interval setting 8-bit f96h?f97h fa8h?fa9h 8-bit write-only ffh toe0 toe1 flag controls timer/counters output to the tclon pin 1-bit f92h.2 f92h.3 1-, 4-bit read/write "0"
timers and timer/counters s3p 7588x 12- 12 clocks set clock selector 8-bit comparator tcntn clear tcln trefn clear irqtn toln tclon p2.0/p9.1 latch toen pm2.0/pm9.1 tmodn.7 tmodn.6 tmodn.5 tmodn.4 tmodn.3 tmodn.2 tmodn.1 tmodn.0 inverted 8 8 8 4 figure 12-2. tc circuit diagram tc enable/disable procedure enable timer/counter ? set tmodn.2 to logic one ? set the tc interrupt enable flag ietn to logic one ? set tmodn.3 to logic one tcntn and irqtn are cleared to logic zero, and timer/counter operation starts. disable timer/counter ? set tmodn.2 to logic zero clock signal input to the counter register tcntn is halted. the current tcntn value is retained and can be read if necessary.
s3p7588x microcontroller ( preliminary ) timers and timer/counters 12- 13 tc programmable timer/counter function timer/counters can be programmed to generate interrupt requests at various intervals based on the selected system clock frequency. its 8-bit tc mode register tmodn is used to activate the timer/counter and to select the clock frequency. the reference register trefn stores the value for the number of clock pulses to be generated between interrupt requests. the counter register, tcntn, counts the incoming clock pulses, which are compared to the trefn value as tcntn is incremented. when there is a match (trefn = tcntn), an interrupt request is generated. to program timer/counter to generate interrupt requests at specific intervals, choose one of four internal clock frequencies (divisions of the system clock, fx) and load a counter reference value into the reference register. the count register is incremented each time an internal counter pulse is detected with the reference clock frequency specified by tmodn.4?tmodn.6 settings. to generate an interrupt request, the tc interrupt request flag (irqtn) should be set to logic one, the status of toln is inverted, and the interrupt is generated. the content of the counter register is then cleared to 00h and tc continues counting. the interrupt request mechanism for tc includes an interrupt enable flag (ietn) and an interrupt request flag (irqtn). tc operation sequence the general sequence of operations for using tc can be summarized as follows: 1. set tmodn.2 to "1" to en able tc0 and tc1 2. set tmodn.6 to "1" to enable the system clock (fx) input 3. set tmodn.5 and tmodn.4 bits to desired internal frequency (fx/2 n ) 4. load a value to trefn to specify the interval between interrupt requests 5. set the tc interrupt enable flag (ietn) to "1" 6. set tmodn.3 bit to "1" to clear tcntn and irqtn, and start counting 7. tcntn increments with each internal clock pulse 8. when the comparator shows tcntn = trefn, the irqtn flag is set to "1" 9. output latch (toln) logic toggles high or low 10. interrupt request is generated 11. tcntn is cleared to 00h and counting resumes 12. programmable timer/counter operation continues until tmodn.2 is cleared to "0".
timers and timer/counters s3p 7588x 12- 14 tc event counter function timer/counters can monitor or detect system 'events' by using the external clock input at the tcln pin as the counter source. the tc mode register selects rising or falling edge detection for incoming clock signals. the counter register is incremented each time the selected state transition of the external clock signal occurs. with the exception of the different tmodn.4?tmodn.6 settings, the operation sequence for tc's event counter function is identical to its programmable timer/counter function. to activate the tc event counter function, ? set tmodn.2 to "1" to enable tc; ? clear tmodn.6 to "0" to select the external clock source at the tcln pin; ? select tcln edge detection for rising or falling signal edges by loading the appropriate values to tmodn.5 and tmodn.4. ? p3.0 and p3.1 must be set to input mode. table 12-5. tmodn settings for tcln edge detection tmodn.5 tmodn.4 tcln edge detection 0 0 rising edges 0 1 falling edges
s3p7588x microcontroller ( preliminary ) timers and timer/counters 12- 15 tc clock frequency output using timer/counters, a modifiable clock frequency can be output to the tc clock output pin, tclon. to select the clock frequency, load the appropriate values to the tc mode register, tmodn. the clock interval is selected by loading the desired reference value into the reference register trefn. in summary, the operational sequence required to output a tc-generated clock signal to the tclon pin is as follows: 1. load a reference value to trefn. 2. set the internal clock frequency in tmodn. 3. initiate tcn clock output to tclon (tmodn.2 = "1"). 4. set port 2, port9 mode flag (pm2.0 and pm 9.1) to "1". 5. set p2.0 and p9.1 output latches to "0". 6. set toen flag to "1". each time the contents of tcntn and trefn coincide and an interrupt request is generated, the state of the output latch toln is inverted and the tc-generated clock signal is output to the tclon pin. f f programming tip ? tc0 signal output to the tclo0 pin output a 30 ms pulse width signal to the tclo0 pin: bits emb smb 15 ld ea,#68h ld tref0,ea ld ea,#4ch ld tmod0,ea ld ea,#01h ld pmg1,ea ; p2.0 ? output mode bitr p2.0 ; p2.0 clear bits toe0
timers and timer/counters s3p 7588x 12- 16 tc external input signal divider by selecting an external clock source and loading a reference value into the tc reference register, trefn, you can divide the incoming clock signal by the trefn value and then output this modified clock frequency to the tclon pin. the sequence of operations used to divide external clock input can be summarized as follows: 1. load a signal divider value to the trefn register 2. clear tmodn.6 to "0" to enable external clock input at th e tcln pin 3. set tmodn.5 and tmodn.4 to desired tcln signal edge detection 4. set port 2, port 9 mode flag (pm2.0, pm9.1) to output ("1") 5. set p2.0 and p9.1 output latches to "0" 6. set toen flag to "1" to enable output of the divided frequency to the tclon pin f f programming tip ? external tcl0 clock output to the tclo0 pin output external tcl0 clock pulse to the tclo0 pin (divide by four): external (tcl0) clock pulse tclo0 output pulse bits emb smb 15 ld ea,#01h ld tref0,ea ld ea,#0ch ld tmod0,ea ld ea,#01h ld pmg1,ea ; p2.0 ? output mode bitr p2.0 ; p2.0 clear bits toe0
s3p7588x microcontroller ( preliminary ) timers and timer/counters 12- 17 tc mode register (tmod n ) tmodn are the 8-bit mode control registers for timer/counter 0 and 1. they are addressable by 8-bit write instructions. one bit, tmodn.3, is also 1-bit writeable. reset clears all tmodn bits to logic zero and disables tc operations. f90h tmod0.3 tmod0.2 "0" "0" tmod0 f91h "0" tmod0.6 tmod0.5 tmod0.4 fa0h tmod1.3 tmod1.2 "0" "0" tmod1 fa1h "0" tmod1.6 tmod1.5 tmod1.4 tmodn.2 is the enable/disable bit for timer/counter 0 and 1. when tmodn.3 is set to "1", the contents of tcntn and irqtn are cleared, counting starts from 00h, and tmodn.3 is automatically reset to "0" for normal tc operation. when tc operation stops (tmodn.2 = "0"), the contents of the counter register tcntn are retained until tc is re-enabled. the tmodn.6, tmodn.5, and tmodn.4 bit settings are used together to select the tc clock source. this selection involves two variables: ? synchronization of timer/counter operations with either the rising edge or the falling edge of the clock signal input at the tcln pin, and ? selection of one of four frequencies, based on division of the incoming system clock frequency, for use in internal tc operation. table 12-6. tc mode register (tmodn) organization bit name setting resulting tc0 function address tmodn.7 0 always logic zero f91h (tmod0) tmodn.6 0,1 specify input clock edge and internal frequency fa1h (tmod1) tmodn.5 tmodn.4 tmodn.3 1 clear tcntn and irqtn. toln is remained and resume counting immediately (this bit is automatically cleared to logic zero immediately after counting resumes.) f90h (tmod0) fa0h (tmod1) tmodn.2 0 disable timer/counter; retain tcntn contents 1 enable timer/counter tmodn.1 0 always logic zero tmodn.0 0 always logic zero
timers and timer/counters s3p 7588x 12- 18 table 12-7. tmodn.6, tmodn.5, and tmodn.4 bit settings tmodn.6 tmodn.5 tmodn.4 tc0 counter source tc1 counter source 0 0 0 external clock input (tcl0) on rising edges external clock input (tcl1) on rising edges 0 0 1 external clock input (tcl0) on falling edges external clock input (tcl1) on falling edges 1 0 0 fx/2 10 (4.09khz) fx/2 12 (1.02khz) 1 0 1 fx /2 6 (65.5khz) fx /2 10 (4.09khz) 1 1 0 fx/2 4 (262khz) fx/2 8 (16.4khz) 1 1 1 fx = 4.19mhz fx/2 6 (65.5khz) note : ' fx' = system clock of 4.19mhz. f f programming tip ? restarting tc0 counting operation 1. set tc0 timer interval to 4.09khz: bits emb smb 15 ld ea,#4ch ld tmod0,ea ei bits iet0 2. clear tcnt0 and irqt0, tol0 is remained and restart tc0 counting operation: bits emb smb 15 bits tmod0.3
s3p7588x microcontroller ( preliminary ) timers and timer/counters 12- 19 tc counter register (tcnt n ) the 8-bit counter register for tc, tcntn, is read-only and can be addressed by 8-bit ram control instructions. reset sets all counter register values to logic zero (00h). whenever tmodn.3 is enabled, tcntn is cleared to logic zero and counting resumes. the tcntn register value is incremented each time an incoming clock signal is detected that matches the signal edge and frequency setting of the tmodn register (specifically, tmodn.6?tmodn.4). each time tcntn is incremented, the new value is compared to the reference value stored in the reference register, trefn. when tcntn = trefn, an overflow occurs in the counter register, the interrupt request flag, irqtn, is set to logic one, and an interrupt request is generated to indicate that the specified timer/counter interval has elapsed. reference value = n 0 n ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ n count clock trefn tcntn ~ ~ interval time toln timer start instruction (tmodn.3 is set) irqtn set irqtn set 1 2 n-1 0 1 2 n-1 0 1 2 3 match match ~ ~ figure 12-3. tc timing diagram
timers and timer/counters s3p 7588x 12- 20 tc reference register (tref n ) the tc reference register, trefn, is an 8-bit write-only register. reset initializes the trefn value to 'ffh'. trefn is used to store a reference value to be compared to the incrementing tcntn register in order to identify an elapsed time interval. reference values will differ depending upon the specific function that tc is being used to perform ? as a programmable timer/counter, event counter, clock signal divider, or arbitrary frequency output source. during timer/counter operation, the value loaded into the reference register is compared to the counter value. when tcntn = trefn, the tc output latch (toln) is inverted and an interrupt request is generated to signal the interval or event. the trefn value, together with the tmodn clock frequency selection, determines the specific tc timer interval. use the following formula to calculate the correct value to load to the trefn reference register: tc timer interval = ( trefn value + 1) 1 tmodn frequency setting (assuming a trefn value 1 0) the 1-bit timer/counter output enable flag toen controls output from timer/counter to the tclon pin. toen is addressable by 1-bit read and write instructions. bit 3 bit 2 bit 1 bit 0 f92h toe1 toe0 boe 0 when you set the toen flag to "1", the contents of toln can be output to the tclon pin. whenever a reset occurs, toen is automatically set to logic zero, disabling all tc output. tc output latch (tol n ) toln is the output latch for timer/counter 0 and 1. when the 8-bit comparator detects a correspondence between the value of the counter register tcntn and the reference value stored in the trefn register, the toln value is inverted ? the latch toggles high-to-low or low-to-high. whenever the state of toln is switched, the tc signal is output. tc output is directed to the tclon pin. assuming tc is enabled, when bit 3 of the tmodn register is set to "1", the toln latch is remained, the counter register, tcntn and the interrupt request flag, irqtn are cleared, and counting resumes immediately. when tcn is disabled (tmodn.2 = "0"), the contents of the toln latch are retained and can be read, if necessary.
s3p7588x microcontroller ( preliminary ) timers and timer/counters 12- 21 f f programming tip ? setting a tc0 timer interval to set a 30ms timer interval for tc0, given fx = 3.58mhz, follow these steps. 1. select the timer/counter 0 mode register with a maximum setup time of 73.3ms (assume the tc0 counter clock = fx/2 10 , and tref0 is set to ffh): 2. calculate the tref0 value: 30 ms = tref0 value + 1 3.49 khz tref0 + 1 = 30 ms 286 s = 104.8 = 69h tref0 value = 69h ? 1 = 68h 3. load the value 68h to the tref0 register: bits emb smb 15 ld ea,#68h ld tref0,ea ld ea,#4ch ld tmod0,ea
timers and timer/counters s3p 7588x 12- 22 watch timer overview the watch timer is a multi-purpose timer consisting of three basic components: ? 8-bit watch timer mode register (wmod) ? clock selector ? frequency divider circuit watch timer functions include real-time and watch-time measurement and interval timing for the system clock. it is also used as a clock source for generating buzzer output. real-time and watch-time measurement to start watch timer operation, set bit 2 of the watch timer mode register, wmod.2, to logic one. the watch timer starts, the interrupt request flag irqw is automatically set to logic one, and interrupt requests commence in 0.5- second intervals. since the watch timer functions as a quasi-interrupt instead of a vectored interrupt, the irqw flag should be cleared to logic zero by program software as soon as a requested interrupt service routine has been executed. using a system clock source the watch timer can generate interrupts based on the system clock frequency. the system clock (fx) is used as the signal source, according to the following formula: watch timer clock( fw) = main system clock(fx) 128 = 32.768 khz (assuming fx = 4.19 mhz) buzzer output frequency generator the watch timer can generate a steady 2khz, 4khz, 8khz, or 16khz signal at 4.19mhz to the buz pin. to select the buz frequency you want, load the appropriate value to the wmod register. this output can then be used to actuate an external buzzer sound. to generate a buz signal, three conditions must be met: ? the wmod.7 register bit is set to "1" ? the output latch for i/o port 2.3 is cleared to "0" ? the port 2.3 output mode flag (pm2.3) set to 'output' mode
s3p7588x microcontroller ( preliminary ) timers and timer/counters 12- 23 timing tests in high-speed mode by setting wmod.1 to "1", the watch timer will function in high-speed mode, generating an interrupt every 3.91ms at 4.19mhz. at its normal speed (wmod.1 = "0"), the watch timer generates an interrupt request every 0.5 seconds. high-speed mode is useful for timing events for program debugging sequences. fw/2 fw/8 fw/16 enable/ disable irqw fw/2 14 fw/2 7 fw (32.768 khz) fx = system clock (assumed to be 4.19 mhz) fw = watch timer frequency mux clock selector gnd fx/128 fw/4 frequency dividing circuit wmod.7 0 wmod.5 wmod.4 0 wmod.2 wmod.1 0 8 buz p2.3 latch pm2.3 selector circuit figure 12-4. watch timer circuit diagram
timers and timer/counters s3p 7588x 12- 24 watch timer mode register (wmod) the watch timer mode register wmod is used to select specific watch timer operations. it is 8-bit write-only addressable. f88h ?0? wmod.2 wmod.1 ?0? f89h wmod.7 "0" wmod.5 wmod.4 wmod settings control the following watch timer functions: ? watch timer speed control (wmod.1) ? enable/disable watch timer (wmod.2) ? buzzer frequency selection (wmod.4 and wmod.5) ? enable/disable buzzer output (wmod.7) table 12-8. watch timer mode register (wmod) organization bit name values function address wmod.7 0 disable buzzer (buz) signal output 1 enable buzzer (buz) signal output wmod.6 0 always logic zero f89h wmod.5 ? .4 0 0 fw/16 buzzer (buz) signal output (2khz) 0 1 fw/8 buzzer (buz) signal output (4khz) 1 0 fw/4 buzzer (buz) signal output (8khz) 1 1 fw/2 buzzer (buz) signal output (16khz) wmod.3 0 always logic zero wmod.2 0 disable watch timer; clear frequency dividing circuits 1 enable watch timer f88h wmod.1 0 normal mode; sets irqw to 0.5 seconds 1 high-speed mode; sets irqw to 3.91 ms wmod.0 0 always logic zero note : system clock frequency (fx) is assumed to be 4.19mhz. ' fw' = watch timer clock frequency.
s3p7588x microcontroller ( preliminary ) timers and timer/counters 12- 25 f f programming tip ? using the watch timer 1. select a 0.5 second interrupt, and 2khz buzzer enable: bits emb smb 15 ld ea,#08h ld pmg1,ea ; p2.3 ? output mode bitr p2.3 ; clear p2.3 output latch ld ea,#84h ld wmod,ea bits iew 2. sample real-time clock processing method: clock btstz irqw ; 0.5 second check ret ; no, return ? ; yes, 0.5 second interrupt generation ? ? ; increment hour, minute , second
timers and timer/counters s3p 7588x 12- 26 notes
s3p7588x dtmf generator 13- 1 13 dtmf generator overview the dual-tone multi-frequency (dtmf) output circuit is used to generate 16 dual-tone multiple frequency signals for tone dialing. this function is controlled by the dtmf mode register(dtmr) or by writing caller id register with serial interfacing. that is, there are two method to control dtmf generator, one is to use caller id register and the other is to use memory mapped register of dtmf generator. there are only memory mapped registers described in this chapter. please refer to chapter 7 to know about the caller id registers. it is recommended to use caller id?s register because you?d better to use s3p7588x?s dtmf output rather than ks57c5208/ks57c5308 smds?s dtmf output. when you develop your own application system by setting s3p7588x as caller id mode (refer to chapter 7), all registers except that of caller id are unable to be used, so if you use memory mapped register of dtmf generator, smds?s dtmf generator is activated instead of s3p7588x?s one. by writing the contents of the output latch for dtmf circuit with output instructions, 16 dual or single tones can be output to the dtmf output pin. the tone output frequency is selected by the dtmf mode register, and tone output amplitude is controlled by dtmf gain register. figure 13-1 shows the dtmf block diagram. a frequency of 3.58 mhz is used for dtmf generator. clock output is inhibited when dtmr.0 (dtmf enable bit) goes low. the tone output has a pdm format, so rc filter is required to get a real dtmf tone wave form. the decoder receives data from the data latch and outputs the result to the row and column tone counter. the row and column tone counter are incremented until new data is latched. when dtmr.0 is logic one, data is latched, and the tone output is changed. table 13-2 shows the 16 available keyboard frequencies. dtmf mode register mode decorder clock sync circuit row counter tone mode control column counter internal bus sine table high multiply & adder sine table low pdm generator tone output f syclk 3.579545 mhz figure 13-1. block diagram of dtmf generator
dtmf generator s3p7 588x 13- 2 table 13-1. keyboard arrangement 1 2 3 a row1 4 5 6 b row2 7 8 9 c row3 * 0 # d row4 column 1 column 2 column 3 column 4 table 13-2. tone output frequencies input specified frequency (hz) actual frequency (hz) % error row1 697 699.1 + 0.31 row2 770 766.2 ? 0.49 row3 852 847.4 ? 0.54 row4 941 948.0 + 0.74 column 1 1209 1215.7 + 0.57 column 2 1336 1331.7 ? 0.32 column 3 1477 1471.7 ? 0.35 column 4 1633 1645.0 + 0.73 dtmf mode register dtmf output is controlled by the dtmf mode register. bit position dtmr.0 enables or disables dtmf operation. if dtmr.0 = 1, dtmf operation is enabled. programmers should write zeros or ones to bit positions dtmr.4?dtmr.7 according to the keyboard input specification. writing the data in a look-up table is useful for program efficiency. the dtmr register is a write- only register, and is manipulated using 8-bit ram control instructions. table 13-3. dtmf mode register (dtmr) organization bit name setting resulting dtmf function address dtmr.7?.4 0,1 specify according to keyboard fd3h dtmr.3 ? not applicable fd2h dtmr.2?.1 0 0 dual-tone enable 1 0 0 1 single-column tone enable 1 1 single-low tone enable dtmr.0 0 disable dtmf operation 1 enable dtmf operation
s3p7588x dtmf generator 13- 3 table 13-4. dtmr.7?dtmr.4 key input control settings dtmr.7 dtmr.6 dtmr.5 dtmr.4 keyboard 0 0 0 0 d 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 0 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 0 0 0 8 1 0 0 1 9 1 0 1 0 0 1 0 1 1 * 1 1 0 0 # 1 1 0 1 a 1 1 1 0 b 1 1 1 1 c when you want to use the caller id register, dtmr register should be zero (the reset value of dtmr) ahead. dtmf gain register dtmf output amplitude is controlled by the dtmf gain register. reset value is 10000b and this means that dtmf output is amplified by 1. the dtgr register is a write-only register, and is manipulated using 8-bit ram control instructions. when you want to use the caller id register, dtgr register should be 10000b (the reset value of dtgr) ahead. table 13-5. dtmf gain register (dtgr) organization bit name setting resulting dtmf function address dtgr.4?.0 0,1 specify amplification factor. dtmf tone output is amplified by (dtgr.4-0 / 16) fd5, fd4h rc filtering dtmf output has a pdm format, so rc filtering is needed to make real dtmf tone wave. recommended value of r and c is as follows. r: 2k w , c: 10nf to see additional information about dtmf application, please refer to chapter 7.
dtmf generator s3p7 588x 13- 4 notes
s3p7588x electrical data 14- 1 14 electrical data overview in this section, information on s3p7588x electrical characteristics is presented as tables and graphics. the information is arranged in the following order: standard electrical characteristics ? absolute maxi mum ratings ? d.c. electrical characteristics ? system clock oscillator characteristics ? i/o capacitance ? a.c. electrical characteristics ? operating voltage range miscellaneous timing waveforms ? a.c timing measurement point ? clock timing measurement at x in and x out ? tcl timing ? input timing for reset ? input timing for external interrupts ? serial data transfer timing stop mode characteristics and timing waveforms ? ram data retention supply voltage in stop mode ? stop mode release timing when initia ted by reset ? stop mode release timing when initiated by an interrupt request
electrical data s3p 7588x 14- 2 table 14-1. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating units supply voltage v dd ? ? 0.3 to + 6.5 v input voltage v i1 all i/o ports ? 0.3 to v dd + 0.3 v output voltage v o ? ? 0.3 to v dd + 0.3 v output current high i oh one i/o port active ? 15 ma all i/o ports active ? 35 output current low i ol one i/o port active + 30 (peak value) ma + 15 (note) all i/o ports active + 100 (peak value) + 60 (note) operating temperature t a ? 0 to + 70 c storage temperature t stg ? 0 to + 70 c note: the values for output current low ( i ol ) are calculated as peak value duty . table 14-2. d.c. electrical characteristics (t a = 0 c to + 70 c, v dd = 2.7v to 5.5v) parameter symbol conditions min typ max units input high voltage v ih1 all input pins except those specified below for v ih2 ? v ih3 0.7 v dd ? v dd v v ih2 ports 1, 3, 6, 7, and reset 0.8 v dd v dd v ih3 xin and xout v dd ? 0.1 v dd input low voltage v il1 all input pins except those specified below for v il2 ? v il3 ? ? 0.3 v dd v v il2 ports 1, 3, 6, 7, and reset 0.2 v dd v il3 x in and x out 0.1
s3p7588x electrical data 14- 3 table 14-2. d.c. electrical characteristics (continued) (t a = 0 c to + 70 c, v dd = 2.7v to 5.5v) parameter symbol conditions min typ max units output high voltage v oh i oh = ? 1ma ports except 1 v dd ? 1.0 ? ? v output low voltage v ol1 v dd = 4.5v to 5.5v i ol = 6ma, ports 4 and 5 only ? 0.4 2 v v dd = 2.7 to 5.5v, i ol = 1.6ma ? ? 0.4 v ol2 v dd = 4.5v to 5.5v i ol = 4ma, all out ports except 4, 5 ? ? 2 v v dd = 2.7 to 5.5 v, i ol = 1.6ma ? ? 0.4 v ol3 v dd = 4.5v to 5.5v i ol = 1ma, dtmf ? ? 2 v v dd = 2.7 to 5.5v, i ol = 1.6ma ? ? 0.4 input high leakage current i lih1 v i = v dd all input pins except those specified below ? ? 3 a i lih2 v i = v dd xin and xout 20 input low leakage current i lil1 v i = 0v all input pins except below and reset ? ? ? 3 a i lil2 v i = 0v x i n and xout only ? 20 output high leakage current i loh v o = v dd all out pins ? ? 3 a output low leakage current i lol v o = 0v xin and xout only ? ? ? 3 a pull-up resistor r l1 v dd = 5v; v i = 0v except reset 25 47 100 k w v dd = 3v 50 95 200 r l2 v dd = 5v; v i = 0v; reset 100 220 400 v dd = 3v 200 450 800
electrical data s3p 7588x 14- 4 table 14-2. d.c. electrical characteristics (continued) (t a = 0 c to + 70 c, v dd = 2.7v to 5.5v) parameter symbol conditions min typ max units supply current (note 1) i dd1 (fsk on) run mode; v dd = 5v 10% (note 2) 3.58mhz crystal oscillator, c1 = c2 = 22pf ? 9.0 11.0 ma vdd = 3 v 10% 6.0 8.0 i dd2 (cas on) run mode; v dd = 5v 10% (note 2) 3.58mhz crystal oscillator, c1 = c2 = 22pf ? 9.9 12.1 ma v dd = 3v 10% 6.6 8.8 i dd3 (cas/fsk off) run mode; v dd = 5v 10% crystal oscillator, c1 = c2 = 22pf 3.58mhz 7.2 8.5 ma v dd = 3v 10% 3.58mhz 5.2 6.9 i dd4 idle mode; = v dd = 5v 10% 3.58mhz 2.5 3.5 ma crystal oscillator, c1 = c2 = 22pf v dd = 3v 10% 3.58mhz 1.2 2.2 i dd5 stop mode; v dd = 5v 10% ? 0.1 3 a stop mode; v dd = 3v 10% 0.1 2 notes: 1. d.c. electrical values for supply current (i dd1 to i dd3 ) do not include current drawn through internal pull-up registers. 2. for d.c. electrical values, the power control register (pcon) must be set to 0011b.
s3p7588x electrical data 14- 5 table 14-3. main system clock oscillator characteristics (t a = 0 c to + 70 c, v dd = 2.7v to 5.5v) oscillator clock configuration parameter test condition min typ max units ceramic oscillator xin c1 c2 xout oscillation frequency (note 1) v dd = 2.7v to 5.5v 0.4 ? 6.0 mhz stabilization time (note 2) v dd = 2.7v ? ? 4 ms crystal oscillator xin c1 c2 xout oscillation frequency (note 1) v dd = 2.7v to 5.5v 0.4 ? 6.0 mhz stabilization time (note 2) v dd = 2.7v ? ? 10 ms external clock xin xout x in input frequency (note 1) v dd = 2.7v to 5.5v 0.4 ? 6.0 mhz x in input high and low level width (t xh , t xl ) ? 83.3 ? 1250 ns notes: 1. oscillation frequency and x in input frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated.
electrical data s3p 7588x 14- 6 table 14-4. input/output capacitance (t a = 25 c, v dd = 0v) parameter symbol condition min typ max units input capacitance c in f = 1mhz; unmeasured pins are returned to v ss ? ? 15 pf output capacitance c out ? ? 15 pf i/o capacitance c io ? ? 15 pf table 14-5. a.c. electrical characteristics (t a = 0 c to + 70 c, v dd = 2.7v to 5.5v) parameter symbol conditions min typ max units instruction cycle time (note 1) t cy v dd = 2.7v to 5.5v 0.67 ? 64 s tcl0, tcl1 input frequency f ti0 , f ti1 v dd = 2.7v to 5.5v 0 ? 1.5 mhz tcl0, tcl1 input high, low width t tih0 , t til0 t tih1 , t til1 v dd = 2.7v to 5.5v 0.48 ? ? s interrupt input high, low width t inth , t intl int1, int2, int4, ks0?ks7 0.1 ? ? s reset input low width t rsl input 0.5 ? ? s
s3p7588x electrical data 14- 7 table 14-6. ram data retention supply voltage in stop mode (t a = 0 c to + 70 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr ? 1.5 ? 5.5 v data retention supply current i dddr v dddr = 1.5v ? 0.1 10 a release signal set time t srel ? 0 ? ? s oscillator stabilization wait time (note 1) t wait released by reset released by interrupt ? 2 17 / fx (note 2) ? ms ms notes: 1. during oscillator stabilization wait time, all cpu operations must be stopped to avoid instability during oscillator start-up. 2. use the basic timer mode register (bmod) interval timer to delay execution of cpu instructions during the wait time.
electrical data s3p 7588x 14- 8 timing waveforms execution of stop instruction v dddr ~ ~ data retention mode v dd ~ ~ stop mode idle mode t srel reset internal reset operating t wait operating mode figure 14-1. stop mode release timing when initiated by reset reset execution of stop instruction v dddr ~ ~ data retention mode v dd ~ ~ stop mode idle mode t srel t wait normal operating mode power-down mode terminating signal (interrupt request) figure 14-2. stop mode release timing when initiated by interrupt request
s3p7588x electrical data 14- 9 timing waveforms (continued) 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd measurement points figure 14-3. a.c. timing measurement points (except for xin) xin t xh t xl 1/fx v dd - 0.1 v 0.1 v figure 14-4. clock timing measurement at xin tcl t tih t til 1/f ti 0.8 v dd 0.2 v dd figure 14-5. tcl timing
electrical data s3p 7588x 14- 10 reset t rsl 0.2 v dd figure 14-6. input timing for reset reset signal int0, 1, 2, 4 k0 to k7 t inth t intl 0.8 v dd 0.2 v dd figure 14-7. input timing for external interrupts and quasi-interrupts
s3p7588x electrical data 14- 11 table 14-7. electrical characteristics of cid block (t a = 0 c to + 70 c, v dd = 5.0v 5%, x in = 3.579545mhz 0.1%) symbol parameter min typ max unit voltage reference vref reference voltage output 2.25 v cas detector thac input accept threshold (in 600 w load) -38 dbm pic input signal power (in 600 w load) -37 -6 dbm flc low tone frequency 2130 hz fhc high tone frequency 2750 hz d fmaxc maximum frequency deviation -0.6 +0.6 % twc twist -6 6 db fsk receiver pif input signal power (in 600 w load) -38 0 dbm fd data transmission rate frequency 1188 1200 1212 baud fmb mark frequency (bell202) 1188 1200 1212 hz fsb space frequency (bell202) 2178 2200 2222 hz fmv mark frequency (ccitt/v23) 1300 hz fsv space frequency (ccitt/v23) 2100 hz twf twist -10 10 db s/n0 signal to noise ratio (0hz ? 200hz) -25 db s/n1 signal to noise ratio (200hz ? 3.2khz) 6 db s/n3 signal to noise ratio (3.2khz ? 15khz) -25 db stutter dial tone detector bw detection bandwidth 330 440 hz thap input accept threshold (in 600 w load ) -36 -10 dbm dtmf generation pod output signal power (for high tone) - - -7.3 dbm d fmaxd maximum frequency deviation -0.1 +0.1 % thdd total harmonic distortion (0 ~ 6khz) - - 2.5 % s/ nd signal to noise ratio (0 ~ 6khz) -35 dbm
electrical data s3p 7588x 14- 12 table 14-8. cas timing characteristics (t a = 0 c to + 70 c, v dd = 2.7v to 5.5v, x in = 3.579545mhz 0.1% ) parameter symbol min typ max unit cas detection time from cas start t detc 67 ms detection off time from cas end t offc 30 ms cas detection time width t widthc 8 ms line signal sdtdet t offc sdt signal t detc t widthc int figure 14-8. waveform for cas timing characteristics table 14-9. sdt timing characteristics (t a = 0 c to + 70 c, v dd = 2.7v to 5.5v, x in = 3.579545mhz 0.1% ) parameter symbol min typ max unit sdt detection time from sdt start t dets 60 ms detection off time from sdt end t offc 30 ms
s3p7588x electrical data 14- 13 line signal sdtdet t offs sdt signal t dets int figure 14-9. waveform for sdt timing characteristics table 14-10. serial interface timing characteristics (t a = 0 c to + 70 c, v dd = 2.7v to 5.5v, x in = 3.579545mhz 0.1% ) parameter symbol min typ max unit sdt to sck time to start serial interface t start 50 ns sck to sdt time to stop serial interface t stop 50 ns sck low time period t sckl 500 ns sck high time period t sckh 500 ns sdt set-up time t su 50 ns sdt hold time t hd 50 ns
electrical data s3p 7588x 14- 14 sdt sck t start t stop start condition stop condition figure 14-10. timing constraints of start and stop condition sdt sck t su t hd t sckl t sckh figure 14-11. timing of sck and sdt during byte transmission
s3p7588x mechanical data 15- 1 15 mechanical data overview the s3p7588x microcontroller are available in a 100-pin tqfp package (100-tqfp-1414), and a pellet type. 44 pin pellet p9.0 p9.1 p9.2 p1.1 p1.2 p1.4 p2.0 p3.0 p3.1 vdd vss test p3.2 reset p3.3 p4.0 p4.1 p4.2 p4.3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 xout xin p2.3 vref vdda lrin dtmf p7.3 p7.2 p7.1 p7.0 p6.3 p6.2 p6.1 p6.0 p5.3 p5.2 p5.1 p5.0 ins inp inn out vssa vssa 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 42 43 44 45 46 47 figure 15-1. pin diagram of pellet type
mechanical data s3p 7588x 15- 2 100-tqfp-1414 #100 14.00 16.00 0.20 14.00 16.00 0.20 0.08 max 0.127 + 0.073 - 0.037 0-7 #1 0.50 (1.00) 0.45-0.75 0.05-0.15 1.00 0.05 1.20 max 0.20 + 0.07 - 0.03 0.08 max figure 15-2. 100-tqfp-1414 package dimensions
s3p7588x otp 16- 1 16 otp overview the s3p7588x single-chip cmos microcontroller is the otp (one time programmable) version. it has an on- chip eprom instead of masked rom. the eprom is accessed by a serial data format.
otp s3p7588x 16- 2 s3p7588x 100-tqfp-1414 nc v ssa out inn inp ins vref v dda lrin dtmf p7.3/ks7 p7.0/ks4 p6.2/ks2 p6.1/ks1 p6.0/ks0 p5.3 p5.2 p5.1 p5.0 p7.2/ks6 p7.1/ks5 p6.3/ks3 nc nc 17 16 14 13 12 11 10 9 8 7 6 5 4 3 2 1 18 19 20 21 22 23 15 24 25 34 35 37 38 39 40 41 42 43 44 45 46 47 48 49 50 33 32 31 30 29 28 36 27 26 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc p1.3/int4 p2.0/tclo0 p3.1/tcl1/sck v dd v ss x out x in test p2.3/buz p3.2 reset p3.3 p4.0/btco p4.1 p4.2 p4.3 p1.2/int2 p1.1/int1 p9.2/clo p9.1/tclo1 p9.0 nc p3.0/tcl0/sda nc nc figure 16-1. s3p7588x pin assignments (100-tqfp-1414)
s3p7588x otp 16- 3 table 16-1. s3p7588x pin descriptions used to read/write the eprom main chip during programming pin name pin name pin no. i/o function p3.0 sdat 11 i/o serial data pin. output port when reading and input port when writing. can be assigned as a input / push-pull output port. p3.1 sclk 12 i/o serial clock pin. input only pin. test v pp (test) 17 i power supply pin for eprom cell writing (indicates that otp enters into the writing mode). when 12.5v is applied, otp is in writing mode and when 5v is applied, otp is in reading mode. (option) reset reset 20 i chip initialization v dd /v ss v dd /v ss 13/14 i logic power supply pin. v dd should be tied to +5v during programming. table 16-2. s3p7588x features characteristic s3p7588x program memory 8k byte eprom operating voltage (v dd ) 2.4v to 5.5v otp programming mode v dd = 5v, v pp (test) = 12.5v pin configuration 100-tqfp-1414 eprom programmability user program 1 time operating mode characteristics when 12.5v is supplied to the v pp (test) pin of the s3p7588x, the eprom programming mode is entered. the operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in table 16-3 below. table 16-3. operating mode selection criteria v dd v pp (test) reg/ mem mem address (a15-a0) r/ w w mode 5v 5v 0 0000h 1 eprom read 12.5v 0 0000h 0 eprom program 12.5v 0 0000h 1 eprom verify 12.5v 1 0e3fh 0 eprom read protection note: "0" means low level; "1" means high level .
otp s3p7588x 16- 4 start address = first location v dd = 5v, v pp = 12.5v x = 0 program one 1ms pulse increment x x = 10 verify 1 byte last address v dd = v pp = 5v compare all byte device passed fail increment address no verify byte device failed fail fail yes pass no figure 16-2. otp programming algorithm
s3p7588x development tools 17- 1 17 development tools overview s3p7588x contains the 4-bit micom of samsung, and all of samsung?s development system for 4-bit micom is applicable to s3p7588x. the development support system is configured with a host system, debugging tools, and support software. for the host system, any standard computer that operates with ms-windows as its operating system can be used. one type of debugging tool including hardware and software is provided: the in- circuit emulator, openice i500, for 4-bit, 8-bit families of samsung microcontrollers. there are other support softwares that includes debugger, assembler, and a program for setting options. otp s one time programmable microcontroller (otp) for the s3p7588x microcontroller and otp programmer (gang) are now available. development system configuration there are four possible configurations of the s3p7588x development system configuration.
development tools s3p7588x 17- 2 to use probe s3p7588x openice-i500 ibm-pc compatible user's target system rs-232c s3p7588x openice-i500 ibm-pc compatible user's target system rs-232c figure 17-1. s3p7588x development system configuration
s3p7588x development tools 17- 3 to use target board s3p7588x openice-i500 ibm-pc compatible user's target system rs-232c sam4 s3p7588x openice-i500 ibm-pc compatible user's target system rs-232c sam4 figure 17-1. s3p7588x development system configuration (continued)
development tools s3p7588x 17- 4 100 qfp ks57e5200] eva chip figure 17-2. s3p7588x target board diagram
s3p7588x development tools 17- 5 power configuration the power configuration of s3p7588x development system is selected by jp1, jp2, jp3, and s1 as following table. table 17-1. switch settings for power configuration jumper state description jp8 jp6 jp3 on off - s3p7588x target board use 5v (from mds or adapter) - user system use same power source as s3p7588x target board cpu s3p7588x user system user vcc (not connected) vss 5v jp8 jp6 jp3 on off - s3p7588x target board use 5v (from mds or adapter) - user system use different power source from s3p7588x target board cpu s3p7588x user system user vcc (connected) vss 5v jp8 jp6 jp3 on off - s3p7588x target board use 3v (from mds or adapter) - user system use same power source as s3p7588x target board cpu s3p7588x user system user vcc (not connected) vss 3v jp8 jp6 jp3 on off - s3p7588x target board use 3v (from mds or adapter) - user system use different power source from s3p7588x target board cpu s3p7588x user system user vcc (connected) vss 3v
development tools 17- 6 jumper state description jp3 on off - s3p7588x target board use the power source from user system. cpu s3p7588x user system user vcc (connected) vss jumper state description s1 on off when the probe system (68 pin connector - cn1, cn2) is used: switch on s1, and connect j1 jack to 5v adapter, and you can select the 3v or 5v by setting jp6, jp8 appropriately. s1 on when the target board system (100 pin connector - u3) is used: switch off s1, and don?t supply power from j1 jack. you can select the 3v or 5v by setting jp6, jp8 appropriately.
s3p7588x development tools 17- 7 user clock selection the user clock ( xin, xout) for target system can be selected as following table. table 17-2. switch settings for user clock selection jumper state description jp4 swclk xtal to use mds(openice-i500) clock as xin, xout jp4 swclk xtal to use crystal as xin, xout you can use appropriate crystal and capacitors by mounting them at dip1 as follows. when this configuration is used, it is strongly recommended to connect the s3p7588x target board directly to user board (not with cable). 1 2 3 6 note: figure 17-2 shows default settings as follows. - use probe(cn1/cn2) and 5v power adapter and target system uses this same power. - use p8.0 as caller id reset signal. - use mds(openice-i500) clock as xin, xout caller id reset selection there are two options for reset signal of caller id block in s3p7588x chip, and it can be also configured in s3p7588x target board as following table. table 17-3. switch settings for reset signal of caller id jp1 jp2 on off on off select p8.0 as caller id reset (jp1, jp2 must be used exclusively) jp1 jp2 on off on off select p3.1 as caller id reset (jp1, jp2 must be used exclusively)
development tools s3p7588x 17- 8 pin assignment s3p7588x target board has two 50-dip connectors (bh1/bh2) for connecting to user system. these connectors have same pin assignments except that tclo1 and clo output is not monitored at p9.1, p9.2 pin respectively. these signals can be only seen in s3p7588x of otp or mask rom version. this mismatch comes from the compatibility issue between the former mcu version (ks57c5208) and s3p7588x. bh1/bh2 nc nc nc p9.0 p9.1 p9.2 p1.1/int1 p1.2/int2 p1.3/int4 p2.0/tclo0 p3.0/tcl0 p3.1/tcl1 v dd v ss x out x in nc p2.3/buz p3.2 resetb p3.3 p4.0/btco p4.1 p4.2 p4.3 nc nc nc nc v ss out inn inp ins vref v dda lrin dtmf p7.3/ks7 p7.2/ks6 p7.1/ks5 p7.0/ks4 p6.3/ks3 p6.2/ks2 p6.1/ks1 p6.0/ks0 p5.3 p5.2 p5.1 p5.0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 50-pin dip connector figure 17-3. pin assignment of 50-pin dip connector
s3p7588x errata 18- 1 18 errata revision 1.0 this documentation have been released first at 2001. 8. 16. errata list from the first released documentation, the followings have been revised. 2001. 10. 11 it is refined that the ca lled id receiver block has no hardware reset input. the reset signal must be made by software to release the caller id receiver from reset state. (refer chapter 7, 10) 2001. 10. 13 this errata has released. the pin description of ? lrin? pin is added, and that of ?resetb? is revised. 2001. 12. 28 the package options are mentioned that only pellet type can be mass-produced. the electrical data has been revised. the pin mismatch between mds board and s3p7588x is mentioned. 2002. 01. 12 the descr iption for tclo1, clo output are corrected that these output come from p9.1, p9.2 instead of p2.1, p2.2 respectively.
errata s3p7588x 18- 2 notes
(for duplicate copies of this form, and for additional ordering information, please contact your local sa m sung sales representative. samsung sales offices are listed on the back cover of this book.) s3p7 series mask rom order form product description: device number: s3p7__________- ___________(write down the rom code number) product order form: package pellet wafer package type: __________ package marking (check one): standard custom a custom b (max 10 chars) (max 10 chars each line) @ : assembly site code, y : last number of assembly year, ww : week of assembly @ yww device name sec device name @ yww @ yww delivery dates and quantities: deliverable required delivery date quantity comments rom code ? not applicable see rom selection form customer sample risk order see risk order sheet please answer the following questions: f f for what kind of product will you be using this order? new product upgrade of an existing product replacement of an existing product other if you are replacing an existing product, please indicate the former product name ( ) f f what are the main reasons you decided to use a samsung microcontroller in your product? please check all that apply. price product quality features and functions development system technical support delivery on time used same micom before quality of documentation samsung reputation mask charge (us$ / won): ____________________________ customer information: company name: ___________________ telephone number _________________________ signatures: ________________________ __________________________________ (person placing the order) (technical manager)

(for duplicate copies of this form, and for additional ordering information, please contact your local sa m sung sales representative. samsung sales offices are listed on the back cover of this book.) s3p7 series request for production at customer risk customer information: company name: __________________________ ______________________________________ department: ________________________________________________________________ telephone number: __________________________ fax: _____________________________ date: __________________________ risk order information: device number: s3p7________- ________ (write down the rom code number) package: number of pins: ____________ package type: _____________________ intended application: ________________________________________________________________ product model number: __ ______________________________________________________________ customer risk order agreement: we hereby request sec to produce the above named product in the quantity stated below. we believe our risk order product to be in full compliance with all sec production specifications and, to this extent, agree to assume responsibility for any and all production risks involved. order quantity and delivery schedule: risk order quantity: _____________________ pcs delivery schedule: delivery date (s) quantity comments signatures: _______________________________ _________________________________ _____ _ (person placing the risk order) (sec sales representative)

(for duplicate copies of this form, and for additional ordering information, please contact your local sa m sung sales representative. samsung sales offices are listed on the back cover of this book.) s3p7588x mask option selection form device number: s3p7588x-_________ (write down the rom code number) attachment (check one): diskette prom customer checksum: ________________________________________________________________ company name: ____________________________________ ____________________________ signature (engineer): ________________________________________________________________ please answer the following questions: f f application (product model id: _______________________) audio video telecom lcd databank caller id lcd game industrials home appliance office a utomation remocon other please describe in detail its application ___________________________________________________________________________

(for duplicate copies of this form, and for additional ordering information, please contact your local sa m sung sales representative. samsung sales offices are listed on the back cover of this book.) s3p7 series otp factory writing order form (1/2) product d escription: device number: s3 p 7________-________(write down the rom code number) product order form: package pellet w afer if the product order form is package: package type: _____________________ package marking (check one): standard custom a custom b (max 10 chars) (max 10 chars each line) @ : assembly site code, y : last number of assembly year, ww : week of assembly @ yww device name sec device name @ yww @ yww delivery dates and quantity: rom code release date required delivery date of device quantity please answer the following questions: f f what is the purpose of this order ? new product development upgrade of an existing product replacement of an existing microcontroller other if you are replacing an existing microcontroller , please indicate the former microcontroller name ( ) f f what are the main reasons you decided to use a samsung microcontroller in your product? please check all that apply. price product quality features and functions development system technical support delivery on time used same micom before quality of documentation samsung reputation customer information: company name: ___________________ telephone number _________________________ signatures: ________________________ __________________________________ (person placing the order) (technical manager)

(for duplicate copies of this form, and for additional ordering information, please contact your local sa m sung sales representative. samsung sales offices are listed on the back cover of this book.) s3p7588x otp factory writing order form (2/2) device number: s3p7588x-__________(write down the rom code number) customer checksums: _________ ____________________________ _________________________ _ company name: ________________________________________________________________ signature (engineer): ____________________________________ ____________________________ read protection (1) : yes no please answer the following questions: f f are you going to continue ordering this device? yes no if so, how much will you be ordering? _________________ pcs f f application (product model id: _______________________) audio video telecom lcd databank caller id lcd game industrials home appliance office a utomation remocon other please describe in detail its application ___________________________________________________________________________ notes: 1. once you choose a read protection, you cannot read again the programming code from the eprom. 2. otp writing will be executed in our manufacturing site. 3. the writing program is completely verified by a customer . samsung does not take on any responsibility for errors occurred from the writing program.

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